1. Bus update after meeting of 11/11
MAX
LEFT column bus M1
Horizontal striping M2 59
8 wires (6+2*2) Pixel config
6 wires (DLL config)
45 addressNN<0:4> M3
45 pileupNN<0:4>
9 DAQReady
5 ver routes available MQ 29
9 parallel_load<8:0>
9 HitOut<8:0>
9 _HitOut<8:0>
2 Synchronous resets MG LY E1 MA
1 global clock
Power rails
MAX
RIGHT Column Bus M1
Horizontal striping M2 59
10 wires (6+2*2) Pixel config
4 ver routes available
45 addressNN<0:4> M3
45 pileupNN<0:4>
9 DAQReady
3 DLL test signals
2 ver routes available MQ 29
9 parallel_load<8:0>
9 HitOut<8:0>
9 _HitOut<8:0>
2 Calibration strobe MG
Horizontal striping (partial) LY E1 MA
1 global clock
Power rails

2. Update after meeting of 13/10
MAX
LEFT column bus M1
Horizontal striping M2 59
8 wires (6+2*2) Pixel config
6 wires (DLL config)
45 addressNN<0:4> M3
45 pileupNN<0:4>
14 ver routes available MQ 29
9 parallel_load<8:0>
9 HitOut<8:0>
9 _HitOut<8:0>
2 Synchronous resets MG LY E1 MA
1 global clock
Power rails
MAX
RIGHT Column Bus M1
Horizontal striping M2 59
10 wires (6+2*2) Pixel config
4 ver routes available
45 addressNN<0:4> M3
45 pileupNN<0:4>
14 ver routes available MQ 29
9 parallel_load<8:0>
9 HitOut<8:0>
9 _HitOut<8:0>
2 Calibration strobe MG
Horizontal striping (partial) LY E1 MA
1 global clock
Power rails

3. Layout of LEFT side bus

4. Full TDC floorplan (now realistic)
Library:
DEFINE gianlucaLibDK17 /projects/IBM_CMOS8/gtk2010/V3.0/workAreas/gaglieri/gianlucaLibDK17
Cell:
gianlucaLibDK17 EoCLayoutTest layout

5. List of wires in TheBus, 13/10 (wk 41)M1 84 M2 64
8 wires (Pixel configuration)
45 addressNN<0:4>
5 enable channel (??) M3
8 wires (DLL config)
45 pileupNN<0:4>
4 enable channel (??) MQ 32
9 parallel_load
9 HitOut<8:0>
9 _HitOut<8:0> MG LY E1 MA
1 dllRefClk
1 clkSync

6. Following are old slides
Following: old slides
Following are old slides

7. MA
0.007 W/□
Power stripes
Ver E1
Critical signals (clk)
Power stripes
Ver
0.006 W/□
Hor
0.089 W/□ LY
Local routing MG
0.038 W/□
Hor
Regional routing MQ
Ver
0.038 W/□
0.064 W/□
Hor M3
0.064 W/□ M2
Local routing
Ver M1
0.071 W/□
Hor

8. Space for routing buses
Width of the DLL
269 um
Width of the HitRegisters + Edge detector
264 um
Space reserved at column sides and tuning
2 + 2 = 4 um
300 - (269+4) = 27 um
Left for routing of buses on M1, M2, M3, MQ, MG
M1: (27 / ( )) = 84 wires (M1)
M2, M3: (27 / ( )) = 66 wires (M2) + 66 wires (M3)
MQ, MG: (27 / ( )) = 32 wires (MQ) + 32 wires (MG)

9. Signals to route across
1 hitArbiters_reset
9 block<8:0>
9 HitOut<8:0>
9 _HitOut<8:0>
9 reset_pileup_in<8:0>
45 addressNN<4:0>
45 pileupNN<4:0>
1 dllrefclk
1 dllreset
1 forceEarly
1 forceLate
1 forceMUX
8 pixel configuration M1 84
9 ro_clk<8:0> M2 66
1 hitArbiters_reset
45 addressNN<0:4>
9 Block<8:0> M3
1 dllreset
1 forceEarly
1 forceLate
1 forceMUX
45 pileupNN<0:4>
9 reset_pileup_in<8:0> MQ 32
9 HitOut<8:0>
9 _HitOut<8:0> MG
1 (+2) dllrefclk
8 pixel configuration
Horizontal tapping from MQ and return paths, gnd references, shieldings

10. Serial readout of fine code hit registers
9 SerialRO<8:0>
Routed on MQ, vertically, on right side of registers block
9 Sel_MUX<8:0>
Routed on MG (or possibly on MQ), vertically, on right side of registers block
9 ro_clk
Routed on M1, vertically, on left side of registers block
Could it be one wire only?
Would be better

11. Serial readout questions
RO_clk distribution tree design
Is buffering needed or ok? Where to locate ?
Pipelining of Serial Shift registers ok? Strength of driver ok? Buffering needed?

12. HitArbiter container
Encoding of the 9 addressX<0:4> output buses
Reduce from 45 to 27 the lines to route on M2
Worthwhile?

14. First test layout of TDC
Floorplanning
Placed, but not the final placement
Connections not routed yet, but all defined
DRC ok
Dimensions
935 ´ 295 μm (metal edges)
Can be shrunk of few microns in width and tens of microns in height
Inter-column gap >= 5 um
TheBus has all wires
As discussed last meeting
Summary in next slide
Details next meeting
Next
Schematics, connections, really finish this
Verification, verification, verification ...
DLL
Hit register
Encoder
...
Pitch adapter
TheBus
32x buffers
Edge detector
32x buffers
TheBus
Still to be prolonged

15. List of wires in TheBus Split Readout controller optionM1 84 M2 66
8 wires (pixel configuration)
1 global reset
45 addressNN<0:4>
5 enable channel M3
8 wires (DLL state machine config)
1 dllreset
45 pileupNN<0:4>
4 enable channel
1 EdgeDetector bias MQ 32
9 parallel_load
9 HitOut<8:0>
9 _HitOut<8:0>
9 SelMUX (east side) MG
9 DAQ_rdy
1 serialROClk (+1)
9 SerialOut (east side) LY E1
1 dllRefClk, 1 clk_ro: shielded striplines
Split Readout controller option
Readout controller
1 global reset
1 clk_ro
9 DAQ_rdy
9 enable_channel
9 + 9 hit, hit_i
9 parallel_load
9 x 5 address
9 x 5 pileup
DLL control
1 dllrefclk
1 dllreset
1 Bias voltage to EdgeDetector
8 wires for dll state machine configuration (SEU support)
Pixel configuration bus
8 wires for pixel configuration (SEU support)
Serial readout
1 serialRoClk
9 selMUX (east side of registers)
9 serialout (east side of registers)

16. NA62 GTK ASIC update, 28/01/2011

17. Activity during weeks 3 and 4
Layout of TDC well advancing
Layout of bus
Placement and interconnection (routing) of
18 Hit Registers + Encoders + Edge Detectors
2 DLL Buffers
The Bus structure
All these interconnected (see layout blocks)
Many layout refinements at lower level, tie-downs
DRC and Antenna passed by all blocks of the hierarchy

18. List of wires in TheBus, 26/01 (wk 4)M1 84 M2 66
8 wires (pixel configuration)
45 addressNN<0:4>
5 enable channel
1 spare M3
8 wires (DLL state machine config)
45 pileupNN<0:4>
4 enable channel
1 global reset
1 dllreset MQ 32
9 parallel_load
9 HitOut<8:0>
9 _HitOut<8:0>
1 EdgeDetector bias (in the gap)
1 serialROClk (+1) (in the gap)
9 SelMUX (east side) MG
9 DAQ_rdy
9 SerialOut (east side) LY E1
1 dllRefClk, 1 clk_ro: shielded striplines
Split Readout controller option
Readout controller
1 global reset
1 clk_ro
9 DAQ_rdy
9 enable_channel
9 + 9 hit, hit_i
9 parallel_load
9 x 5 address
9 x 5 pileup
DLL control
1 dllrefclk
1 dllreset
1 Bias voltage to EdgeDetector
8 wires for dll state machine configuration (SEU support)
Pixel configuration bus
8 wires for pixel configuration (SEU support)
Serial readout
1 serialRoClk
9 selMUX (east side of registers)
9 serialout (east side of registers)

19. Hot items (very next) Converge on how to treat substrate connections
Non homogenous treatment, need to converge on best practice, looking forward to later (isolated substrates)
Jan to pontificate on this
This needed for LVS checks
Place and connect Lukas DLL
Further questions
The EdgeDetector uses pbias (slew control). The buffers of the dll lines don't. Is it ok??
Need to know what lines needs to be added to the bus (discussed in a meeting I missed)