1. COSC121: Computer Systems: LC3 I/O (Intro)
Jeremy Bolton, PhD
Assistant Teaching Professor
Constructed using materials:
- Patt and Patel Introduction to Computing Systems (2nd)
- Patterson and Hennessy Computer Organization and Design (4th)
**A special thanks to Rich Squier and Walid Najjar

2. Notes Read PP.8 – PP.9 Complete HW #4 Project #1 Posted (in parts)
Supplemental files

3. Outline Programming in Overview of I/O in LC3 Polling vs Interrupts
Keyboard
Monitor
Polling vs Interrupts
Operating System Intro

4. This week … our journey takes us …
COSC 121: Computer Systems
Application (Browser)
Operating
System
(Win, Linux)
Compiler
COSC 255: Operating Systems
Software
Assembler
Drivers
Instruction Set
Architecture
Hardware
Processor
Memory
I/O system
Datapath & Control
Digital Design
COSC 120: Computer Hardware
Circuit Design
transistors

5. PP.8 I/O

6. I/O: Connecting to Outside World
So far, we’ve learned how to:
compute with values in registers
load data from memory to registers
store data from registers to memory
But where does data in memory come from?
And how does data get out of the system so that humans can use it?

7. I/O Basics Definitions LC-3 supports only a keyboard and a monitor
Input
transfer data from the outside world to the computer:
keyboard, mouse, scanner, bar-code reader, etc.
Output
transfer data from the computer to the outside:
monitor, printer, LED display, etc.
Peripheral: any I/O device, including disks.
LC-3 supports only a keyboard and a monitor

8. I/O: Connecting to the Outside World
Types of I/O devices characterized by:
behavior: input, output, storage
input: keyboard, motion detector, network interface
output: monitor, printer, network interface
storage: disk, CD-ROM
data rate: how fast can data be transferred?
keyboard: 100 bytes/sec
disk: 30 MB/s
network: 1 Mb/s - 1 Gb/s

9. Device Registers I/O Interface LC-3 Through a set of Device Registers:
Status register (device is busy/idle/error)
Data register (data to be moved to/from device)
The device registers have to be read/written by the CPU.
LC-3
KBDR: keyboard data register
KBSR: keyboard status register
DDR: display data register
DSR: display status register
KBSR[15] - keyboard ready (new character available)
KBDR[7:0] - character typed (ASCII)
DSR[15] - monitor ready
DDR[7:0] - character to be displayed (ASCII)
LC-3
KBSR
KBDR
DSR
DDR

10. Communication with I/O devices
Each IO device will have a controller to facilitate communication.
Communication is facilitated through a shared medium
Memory or direct lines
Interaction with an I/O device is restricted by OS (more to come)
Processor
Memory - I/O Bus
Main
Memory
I/O
Controller
I/O
Controller
I/O
Controller
Monitor
Disk
Disk
Network

11. Memory-Mapped vs. I/O Instructions
Special I/O Instructions
Read or write to device registers using specialized I/O instructions.
Memory Mapped I/O
Use existing data movement instructions (Load & Store).
Map each device register to a memory address (fixed).
CPU communicates with the device registers as if they were memory locations.
LC-3
Uses memory mapped I/O:
xFE00 KBSR Keyboard Status Register
xFE02 KBDR Keyboard Data Register
XFE04 DSR Display Status Register
XFE06 DDR Display Data Register
XFFFE MCR Machine Control Register

12. Memory-Mapped vs. I/O Instructions
designate opcode(s) for I/O
register and operation encoded in instruction
Memory-mapped
assign a memory address to each device register
use data movement instructions (LD/ST) for control and data transfer

13. Synchronizing CPU and I/O
Problem
Speed mismatch between CPU and I/O:
CPU runs at up to ~ 2 GHz, while all I/O is much slower.
Example : Keyboard input is both slow, and irregular.
We need a protocol to keep CPU & KBD synchronized.
Two possible solutions:
Polling (handshake synchronization)
Interrupt-driven I/O

14. Transfer Timing
I/O events generally happen much slower than CPU cycles.
Synchronous
data supplied at a fixed, predictable rate
CPU reads/writes every X cycles
Asynchronous
data rate less predictable
CPU must synchronize with device, so that it doesn’t miss data or write too quickly

15. Transfer Control Who determines when the next data transfer occurs?
Polling
CPU keeps checking status register until new data arrives OR device ready for next data
“Are we there yet? Are we there yet? Are we there yet?”
Interrupts
Device sends a special signal to CPU when new data arrives OR device ready for next data
CPU can be performing other tasks instead of polling device.
“Wake me when we get there.”

16. Polling v/s Interrupts (Who’s driving?)
Polling: CPU in charge
CPU checks the ready bit of status register
(as per program instructions).
If (KBSR[15] == 1) then load KBDR[7:0] to a register.
If the I/O device is very slow, CPU is kept busy waiting.
Interrupt: peripheral in charge
Event triggered - when the I/O device is ready,
it sets a flag called an interrupt.
When an interrupt is set, the CPU is forced to an
interrupt service routine (ISR) which services
the interrupting device.
There can be different priority levels of interrupt.

17. LC-3 Memory-mapped I/O (Table A.3) Asynchronous devices
synchronized through status registers
Polling and Interrupts
the details of interrupts will be discussed in Chapter 10
Location
I/O Register
Function
xFE00
Keyboard Status Reg (KBSR)
Bit [15] is one when keyboard has received a new character.
xFE02
Keyboard Data Reg (KBDR)
Bits [7:0] contain the last character typed on keyboard.
xFE04
Display Status Register (DSR)
Bit [15] is one when device ready to display another char on screen.
xFE06
Display Data Register (DDR)
Character written to bits [7:0] will be displayed on screen.

18. Input from Keyboard When a character is typed: When KBDR is read:
its ASCII code is placed in bits [7:0] of KBDR (bits [15:8] are always zero)
the “ready bit” (KBSR[15]) is set to one
keyboard is disabled -- any typed characters will be ignored**
When KBDR is read:
KBSR[15] is set to zero
keyboard is enabled
keyboard data 15 8 7
KBDR 15 14
ready bit
KBSR

19. Basic Input Routine POLL LDI R0, KBSRPtr BRzp POLL LDI R0, KBDRPtr ...
KBSRPtr .FILL xFE00 KBDRPtr .FILL xFE02
new
char? NO
Polling
YES
read character

20. Output to Monitor When Monitor is ready to display another character:
the “ready bit” (DSR[15]) is set to one
When data is written to Display Data Register:
DSR[15] is set to zero
character in DDR[7:0] is displayed
any other character data written to DDR is ignored (while DSR[15] is zero)
output data 15 8 7
DDR 15 14
ready bit
DSR

21. Basic Output Routine POLL LDI R1, DSRPtr BRzp POLL STI R0, DDRPtr ...
DSRPtr .FILL xFE04 DDRPtr .FILL xFE06
screen
ready? NO
Polling
YES
write character

22. Simple Polling Examples
Why use pointers here?
START LDI R1, A ;Loop if Ready not set
BRzp START
LDI R0, B ;If set, load char to R0
BR NEXT_TASK
A .FILL xFE00 ;Address of KBSR
B .FILL xFE02 ;Address of KBDR
Input a character from keyboard
START LDI R1, A ;Loop if Ready not set
BRzp START
STI R0, B ;If set, send char to DDR
BR NEXT_TASK
A .FILL xFE04 ;Address of DSR
B .FILL xFE06 ;Address of DDR
Output a character to the monitor

23. Example: Print a string
LEA R1, STR ;Load address of string
LOOP LDR R0, R1, #0 ;get next char to R0
BRZ DONE ;string ends with 0
LP LDI R3, DSR ;Loop until MON is ready
BRzp LP2
STI R0, DDR ;Write next character
ADD R1, R1, #1 ; Set address to next char
BR LOOP
STR .STRINGZ "Char String"
DONE HALT

24. Interrupt-driven I/O Generating the interrupt signal
The I/O device must want to request service.
The device must have the right to request service,
This request must be more urgent than the
processor’s current task.
Handling the interrupt signal
We will wait untile we understand stacks
before getting to this.

25. Interrupt-Driven I/O External device can:
Force currently executing program to stop;
Have the processor satisfy the device’s needs; and
Resume the stopped program as if nothing happened.
Why?
Polling consumes a lot of cycles, especially for rare events – these cycles can be used for more computation.
Example: Process previous input while collecting current input. (See Example 8.1 in text.)

26. Generating the Interrupt: More to come later on …
Using the Status Register
The peripheral sets a Ready bit in SR[15] (as with polling)
The CPU sets an Interrupt Enable bit in SR[14]
These two bits are anded to set the Interrupt.
In this way, the CPU has the final say in who gets to interrupt it!

27. Testing for Interrupt Signal
CPU looks at signal between STORE and FETCH phases.
If not set, continues with next instruction.
If set, transfers control to interrupt service routine. F NO D
interrupt
signal?
Transfer to
ISR
YES EA OP EX
More details later! S

28. Jeremy Bolton, PhD Assistant Teaching Professor
Appendix:
Jeremy Bolton, PhD
Assistant Teaching Professor
Constructed using materials:
- Patt and Patel Introduction to Computing Systems (2nd)
- Patterson and Hennessy Computer Organization and Design (4th)
**A special thanks to Rich Squier and Walid Najjar

29. Keyboard Echo Routine
Usually, input character is also printed to screen.
User gets feedback on character typed and knows its ok to type the next character.
new
char?
POLL1 LDI R0, KBSRPtr BRzp POLL1 LDI R0, KBDRPtr POLL2 LDI R1, DSRPtr BRzp POLL2 STI R0, DDRPtr
...
KBSRPtr .FILL xFE00 KBDRPtr .FILL xFE02 DSRPtr .FILL xFE04 DDRPtr .FILL xFE06 NO
YES
read character
screen
ready? NO
YES
write character

30. Priority Every instruction executes at a stated level of urgency.
LC-3: 8 priority levels (PL0-PL7)
Example:
Payroll program runs at PL0.
Nuclear power correction program runs at PL6.
It’s OK for PL6 device to interrupt PL0 program, but not the other way around.
Priority encoder selects highest-priority device, compares to current processor priority level, and generates interrupt signal if appropriate.

31. Device Priority

32. Simple Implementation: Memory-Mapped Input
Address Control Logic
determines whether
MDR is loaded from Memory or from KBSR/KBDR.

33. Full Implementation of LC-3 Memory-Mapped I/O
Because of interrupt enable bits, status registers (KBSR/DSR) must be written, as well as read.