Presentation is loading. Please wait.

Presentation is loading. Please wait.

J. W. Kim and J.D.Cho 성균관대학교 http://vada.skku.ac.kr Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교 http://vada.skku.ac.kr SungKyunKwan Univ.

Similar presentations


Presentation on theme: "J. W. Kim and J.D.Cho 성균관대학교 http://vada.skku.ac.kr Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교 http://vada.skku.ac.kr SungKyunKwan Univ."— Presentation transcript:

1 J. W. Kim and J.D.Cho 성균관대학교 http://vada.skku.ac.kr
Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교 SungKyunKwan Univ.

2 Low Power Equalizer Jin Woo Kim, J.D.Cho, 1999, SKKU Introduction
Low-Power Methodology in Equalizers Simulation Future Work Reference SungKyunKwan Univ.

3 Introduction – xDSL (Digital Subscriber Line)
Provide high bandwidth over copper twisted pair local loop cable, without amplifiers or repeaters Utilize full potential of a copper telephone subscriber loop up to a few hundred times that of a voiceband modem Support industry – standard transmission formats and bit rate such as T1 and E1 SungKyunKwan Univ.

4 Introduction – xDSL Channel Configuration
SungKyunKwan Univ.

5 DMT for ADSL ( Discrete MultiTone Modulation)
Built-in subchannel optimization Ongoing active monitoring Maximum loop variation coverage Highest level of rate flexibility Superior noise immunity for greater throughput Broad industry chipset support Interoperability through standards Virtually future proof SungKyunKwan Univ.

6 DMT SubChannel Allocation for ADSL
#1 ~ #6 : Analog Voice #7 ~ #38 : Upstream Channels #7 ~ #256 : Downstream Channels SungKyunKwan Univ.

7 ADSL Block Diagram ( DMT )
SungKyunKwan Univ.

8 Equalizer – TEQ ( Time Domain Equalizer )
TEQ with a small number of taps can reduce the cyclic prefix(CP) Power Consumption Critical Part Adaptive FIR filters (LMS algorithm) The Filter Output The Filter Coefficient The Error Signal SungKyunKwan Univ.

9 Equalizer – Example of TEQ
SungKyunKwan Univ.

10 Equalizer – FEQ ( Frequency Domain Equalizer )
Compensate for the remaining frequency dependent attenuation and phase rotation of each subchannel Complex One-Tap FIR filter per one subchannel (ADSL ; 256-7) SungKyunKwan Univ.

11 Equalizer – Example of FEQ
LMS(Least Mean Square) Adaptive Filter SungKyunKwan Univ.

12 Low Power Methodology in Equalizers – Circuit
FIR Filter Carry-save adder Grouped Multipliers(Wallace Tree Multiplier) Booth Recoding technique Updating Circuits Power-of-two LMS updating The use of register file Coefficient freezing Make step size constant(m) to power-of-2 SungKyunKwan Univ.

13 Low Power Methodology in Equalizers – Run-time
The Error Monitor Adaptive Bit Precision Burst-Mode Update Adaptive Filter Length SungKyunKwan Univ.

14 Low Power Methodology in Equalizers – Example
SungKyunKwan Univ.

15 Simulation – Environment (1)
Input Sequence PRD(Pseudo Random Sequence) [T1E1.4] Make 4-QAM symbols as Training Sequence SungKyunKwan Univ.

16 Simulation – Environment (2)
Test Channel CSA#6 26AWG(0.4mm) 9000ft(about 2.7Km) AWGN noise environment SNR 40dB SungKyunKwan Univ.

17 Simulation – Channel ( Impulse Response )
SungKyunKwan Univ.

18 Simulation – Before Training ( Received constellation )
SungKyunKwan Univ.

19 Simulation – Before Training ( Coefficient constellation )
SungKyunKwan Univ.

20 Simulation – Before Training ( Output constellation )
SungKyunKwan Univ.

21 Simulation – After Training ( Output constellation )
SungKyunKwan Univ.

22 Simulation – Output SNR
SungKyunKwan Univ.

23 Simulation – Result Analysis
Step Constants(m) are power-of-2 0.5 -> ½ (2-1) > 1/8 (2-3) > 1/32 (2-5) > 1/128 (2-7) The smaller Constant, the longer convergence time Replace Complex Multiplier to Just Exponent Adder Low Power Consumption is acquired SungKyunKwan Univ.

24 Simulation – Using HP ADS Schematic - Transceiver
SungKyunKwan Univ.

25 Simulation – Using HP ADS Schematic - Channel
SungKyunKwan Univ.

26 Simulation – Using HP ADS Schematic - Receiver
SungKyunKwan Univ.

27 Future Work (1) Simulation TEQ simulation NEXT, FEXT Channel Modeling
Attach Cyclic Prefix Echo Canceller Simulation Apply more Low-power Method Apply Auto Bit Loading Transmission Test to 215-QAM SungKyunKwan Univ.

28 Future Work (2) Hardware Synthesis Implement FEQ in VHDL (Synopsys)
Implement TEQ in VHDL (Synopsys) Apply Low-Power algorithm to EQ Verify the function between Classical EQ and Low-Power EQ Compare the power between Classical EQ and Low-Power EQ SungKyunKwan Univ.

29 Future Work (3) Current Simulation and Implementation model is for ADSL, but after improve the Speed and Power, I will apply all the algorithms to VDSL. SungKyunKwan Univ.

30 Reference (1) W. Y. Chen, “DSL”, Macmillan Technical publishing, 1998
W. Goralski, “ADSL and DSL Technologies”, McGraw-Hill, 1998 K. Azadet et al, “Low-Power Equalizer Architectures for High-Speed modems”, IEEE Comm. Magazine, Oct. 1998 C. Nicol et al, “A Low-Power 128-Tap Digital Adaptive Equalizer for Broadband Modems”, IEEE jour. Of Solid-state Circuits, Nov. 1997 SungKyunKwan Univ.

31 Reference (2) H. Lee et al, “A New Hardware-Efficient Architecture for Programmable FIR Filters”, IEEE Trans. On Circuits and Systems, Sep. 1996 J. Rinne et al, “Equalization of Orthogonal Frequency Division Multiplexing Signals”, Proc. Of GLOBECOM’94, pp , Nov 27, 1994 “DSP Solutions for Voiceband and ADSL Modems”, Texas Instrument, June, 1998 SungKyunKwan Univ.


Download ppt "J. W. Kim and J.D.Cho 성균관대학교 http://vada.skku.ac.kr Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교 http://vada.skku.ac.kr SungKyunKwan Univ."

Similar presentations


Ads by Google