1. RUN-TIME PARTIAL RECONFIGURATION SPEED INVESTIGATION AND ARCHITECTURAL DESIGN SPACE EXPLORATION
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch
Review by Gabriel Trevisan

2. Outline Motivation Background Run-time PR with ICAP Results
Run-time Partial reconfiguration
ICAP
Run-time PR with ICAP
Results
Conclusions

3. Motivation
Run-time reconfiguration is essential for reduction in fabric usage and power consumption
Standard methods are not fast enough to ensure right functioning of some functions

4. Introduction – Run-time reconfig.
Run-time reconfiguration happens when a part of an FPGA is reconfigured during the execution of a process.
Many ways of doing so, for example JTAG, which is the serial cable, and ICAP

5. Introduction - ICAP ICAP stands for Internal Configuration Access Port
ICAP interfaces the FPGA configuration memory with this master device and the memories.
A master-device will transmit the reconfiguration information from the memory to the ICAP
Using Virtex 4;

6. ICAP ilustration

7. Sample embedded design
In order to study the PR process, a sample design was built where a partial reconfigurable region (PRR) was placed among other controllers to study the run-time PR

8. Sample embedded architecture
PLB_GPIO – PLB General Purpose I/O core
PR: the processor fetches bitstream data from the memory devices, such as DDR or the non-volatile flash memory, and delivers them to the ICAP design.

9. ICAP Design Evolution – OPB
The OPB_HWICAP is basically composed by:
a protocol adaptation bridge,
a set of dual port block ram (DP_BRAM),
state machines to perform the control.

10. ICAP Design Evolution – OPB

11. ICAP Design Evolution – XPS
In contrast with the OPB_HWICAP design, the XPS_HWICAP has read/write FIFOs replacing the DP_BRAMs
Supports burst modes

12. ICAP Design Evolution – XPS

13. ICAP Design Evolution – DMA
Direct memory access was used
Better data transfer efficiency
Slave interface receive commands, Destination address and length registers
Master transfer data from the memory to the ICAP

14. ICAP Design Evolution – DMA

15. ICAP Design Evolution – MST
The difference between the MST_HWICAP and the DMA_HWICAP is the inclusion of a master device that will fetch data from the memory actively
Communication overhead decreased

16. ICAP Design Evolution – MST

17. ICAP Design Evolution – BRAM
Used to investigate the capabilities of the ICAP primitive
Similar to XPS_HWICAP but instead of FIFOs, a BRAM block is used
Fast, but expensive.

18. ICAP Design Evolution – BRAM

19. Performance Measurements
Xilinx ML405 development board with a Virtex-4 FX-20 FPGA
Bit streams initialized in DDR, except for BRAM_HWICAP
System runs at 100 MHz
PowerPC, PowerPC with cache enable and Microblaze used in tests

20. Performance Measurements
The bottleneck for the MST is the data delivery throughput of the DDR memory, what means that

21. Performance Analysis Timing results
Implementation using DMA increases speed in one order of magnitude
Implementation using MST increases speed even more
DMA and MST are processor independent methods
Bottleneck of MST is in memory throughput

22. Synthesis Measurements
Synthetizing using Xilinx ISE v10.1

23. Synthesis Analysis OPB_HWICAP: light and slow
XPS_HWICAP: uses more LUTs but no BRAMs. Useful only for really limited resources FPGAs
DMA_HWICAP: Good speed, no BRAMs usage, but costly in terms of LUTs
MST_HWICAP: Best resource consumption vs. great speed. Uses 2 BRAMs
BRAM_HWICAP: LUT usage really low, best speed, but really costly in terms of BRAMs

24. Conclusion Clear conclusion Well written Really contributive
Implementation introduction
Comparison among different implementation
Useful topic

25. Questions?