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Top-level Schematics Digital Block Sign-off Digital Model of Chip

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Presentation on theme: "Top-level Schematics Digital Block Sign-off Digital Model of Chip"— Presentation transcript:

1 Top-level Schematics Digital Block Sign-off Digital Model of Chip
Outline of Interactive Session April 16th, 2010 FEI4_A Review - Dario Gnani - LBNL

2 Top-level Schematics Outline General Overview
Science data path Configuration data-path Test system Block-by-block connectivity Status To do list April 16th, 2010 FEI4_A Review - Dario Gnani - LBNL

3 Top-level Schematics ()
© M Karagounis 2010 April 16th, 2010 FEI4_A Review - Dario Gnani - LBNL

4 Top-level Schematics (2)
All fundamental blocks are instantiated and their terminal connected Schematic is updated in tandem with layout and kept LVS clean Higher level schematic maintained and used for verilog-level verification Physical and functional verification are converging All instantiated blocks signed-off individually Netlisting bottleneck in OA OA database shared in real-time April 16th, 2010 FEI4_A Review - Dario Gnani - LBNL

5 Top-level Schematics (3)
TO DO Pad Frame being finalized (Michael) Lower-priority blocks and variants DC-DC, GADC, TEMPSENS,... April 16th, 2010 FEI4_A Review - Dario Gnani - LBNL

6 Digital Block Sign-off
Outline Overview timing functional Block-level results report examples Status April 16th, 2010 FEI4_A Review - Dario Gnani - LBNL

7 Digital Block Sign-off (2)
Digital-level sign-off formal verification (Atul flow, Primetime) RTL vs post-synthesis vs post-P&R timing (STA) (Atul flow, Primetime) OCV derating, SI cross-talk (Atul flow, Primetime SI) CCS-model-based noise sign-off functional simulation functional-level/RTL/behavioral macros (intermediate state during debugging) post-layout/SDF/'timed' macros April 16th, 2010 FEI4_A Review - Dario Gnani - LBNL

8 Digital Block Sign-off (3)
Analog-level sign-off Post-layout SPICE simulations supply lumped parasitics (RC) IR-drop ripple power-up signal distributed parasitics (RCC) Matching w/ SDF delays Verify peak currents and avg power Includes parasitic diodes April 16th, 2010 FEI4_A Review - Dario Gnani - LBNL

9 Digital Model of Chip Outline General Overview Model examples Status
approach implementation description levels Model examples memory efuse pll Status April 16th, 2010 FEI4_A Review - Dario Gnani - LBNL

10 Digital Model of Chip (2)
verilog netlisting from schematics keep schematics as 'golden' reference does not require separate verilog vs schematic verification allows for macro modeling at gate level force all verilog net connections by name cross-view compatibility (RTL/gate-level/behavioral) gate-level macro models minimize reverse-engineering errors maximize implementation checks (paid off) take advantage of std-cell-based sub-blocks requires new reference libraries issues cadence bugs collaboration-wide tool availability constraints April 16th, 2010 FEI4_A Review - Dario Gnani - LBNL

11 Summary Overall Status
Top-level schematic is ready for final integration step (pad frame, minor blocks) Sign-off STA procedure is defined, tested and adopted Full-chip schematic-based gate-level Verilog model is implemented and adopted STA timing libraries for full- custom blocks are under development Full-accuracy fast spice will be used to sign-off a target set of super-blocks and operations (e.g.FEND_COLUMN+DD C and full-chip power-up) April 16th, 2010 FEI4_A Review - Dario Gnani - LBNL

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