1. Digital CMOS Logic Circuits

2. 10.1 Digital Circuit Design: An Overview
Logic-Circuit Characterization: Noise Margin
Noise Margin:
NMH  VOH – VIH
NML  VIL – VOL
Ideal Inverter: NMH = NML = VDD/2

3. 10.1 Digital Circuit Design: An Overview
Logic-Circuit Characterization: Propagation Delay
tP  ½ (tPLH + tPHL)

4. 10.2 Design and Performance Analysis of the CMOS Inverter
Static Operation: sizing the transistor
rDSN=rDSP:
Equal propagation delay
Equal Noise Margin

5. 10.2 Design and Performance Analysis of the CMOS Inverter
Dynamic Operation

6. 10.2 Design and Performance Analysis of the CMOS Inverter
Dynamic Operation

7. 10.3 CMOS Logic-Gate Circuits
Basic Structure

8. 10.3 CMOS Logic-Gate Circuits
Basic Structure (cont.)

9. 10.3 CMOS Logic-Gate Circuits
Basic Structure (cont.)

10. 10.3 CMOS Logic-Gate Circuits
Basic Structure (cont.)
Figure Usual and alternative circuit symbols for MOSFETs.

11. 10.3 CMOS Logic-Gate Circuits
The Two-Input NOR Gate
Figure A two-input CMOS NOR gate.

12. 10.3 CMOS Logic-Gate Circuits
The Two-Input NAND Gate
Figure A two-input CMOS NAND gate.

13. 10.3 CMOS Logic-Gate Circuits
A Complex Gate
Figure CMOS realization of a complex gate.

14. 10.3 CMOS Logic-Gate Circuits
The Exclusive-OR Function

15. 10.3 CMOS Logic-Gate Circuits
Summary
The PDN can be synthesized by expressing as function of the uncomplemented variables. Additional inverter will be required for the complemented variables.
The PUN can be synthesized by expressing as a function of complemented variables. Additional inverter will be required for the uncomplmented variables.
The PDN can be obtained from the PUN from the duality property.

16. Homework:
13.1, 13.6, 13.19, 13.26, 13.28, 13.38, 13.42, 13.45, 13.48