1. Topics
Driving long wires.

2. Wire delay Wires have parasitic resistance, capacitance.
Parasitics start to dominate in deep-submicron wires.
Distributed RC introduces time of flight along wire into gate-to-gate delay.

3. RC transmission line
Assumes that dominant capacitive coupling is to ground, inductance can be ignored.
Elemental values are ri, ci.

4. Elmore delay
Elmore defined delay through linear network as the first moment of the network impulse response.

5. RC Elmore delay Can be computed as sum of sections:
E =  r(n - i)c = 0.5 rcn(n-1)
Resistor ri must charge all downstream capacitors.
Delay grows as square of wire length.
Minimizing rc product minimizes growth of delay with increasing wire length.

6. RC transmission lines More complex analysis. Step response:
1 + K1 exp{-s1t/RC}.

7. Wire sizing
Wire length is determined by layout architecture, but we can choose wire width to minimize delay.
Wire width can vary with distance from driver to adjust the resistance which drives downstream capacitance.

8. Optimal wiresizing Wire with minimum delay has an exponential taper.
Optimal tapering improves delay by about 8%.

9. Approximate tapering
Can approximate optimal tapering with a few rectangular segments.

10. Tapering of wiring trees
Different branches of tree can be set to different lengths to optimize delay.
source
sink 1
sink 2

11. Spanning tree
A spanning tree has segments that go directly between sources and sinks.
source
sink 1
sink 2

12. Steiner tree
A Steiner point is an intermediate point for the creation of new branches.
source
Steiner point
sink 1
sink 2

13. RC trees
Generalization of RC transmission line.

14. Buffer insertion in RC transmission lines
Assume RC transmission line.
Assume R0 is driver’s resistance, C0 is driver’s input capacitance.
Want to divide line into k sections of length l. Each buffer is of size h.

15. Buffer insertion analysis
Assume h = 1:
k = sqrt{(0.4 Rint Cint)/(0.7R0 C0)}
Assume arbitrary h:
h = sqrt{(R0 Cint)/(Rint C0)}
T50% = 2.5 sqrt{R0 C0 Rint Cint}

16. Buffer insertion example
10x minimum-size inverter drives metal 3 wire of 5000 l x 3 l.
Driver: R0 = 11.1 kW, C0 = 1.2 fF
Wire: Rint = 100 W, Cint = 135 fF.
Then
k = 2.4 approx 2.
H = 35.4.
T50% = 11 E-12 sec

17. RC crosstalk Crosstalk slows down signals---increases settling noise.
Two nets in analysis:
aggressor net causes interference;
victim net is interfered with.

18. Aggressors and victims
aggressor net
victim net

19. Wire cross-section Victim net is surrounded by two aggressors. W S T H
substrate

20. Crosstalk delay vs. wire aspect ratio
increased spacing
relative RC delay
Increasing aspect ratio

21. Crosstalk delay
There is an optimum wire width for any given wire spacing---at bottom of U curve.
Optimium width increases as spacing between wires increases.