1. Specific action list following TDC review meeting on 16 March
Summary of Gianluca and Lukas comments

2. Action list Gianluca Action list Gianluca
Checking of DLL, hit register and Encoder designs to confirm selection of the right edge
Consideration of possible revision of encoding logic to keep encoding functional also in case of code with spurious 0 at the last location
Coarse time stamp unit
Verification of RTL design
Synthesis
Verification post synthesis
P&R
Verification plan and test bench for the full TDC
Revision of full TDC once complete
Allocation of powering stripes for the DLL and fine registers section

3. Action list Lukas Action list Lukas
Plot and table of propagation delay vs voltage for all conditions and corners
Remove the bias driving circuit for the edge detector because not needed
Correct documentation for the DE_Vampl parameter. Correct values already distributed by
Current mirrors using transistors with different vt
Lukas made all checks including process and mismatch MC. To discuss with Paulo in a dedicated one to one
Voltage follower for the charge pump to be verified for SSF and FFF corners
Was designed for higher voltage
Comment on 30% of bias current from min bias circuit
To be discussed with Paulo
Adding of low pass RC on min bias
DLL simulation in closed loop
Consider triplication of transistors on reset line
SEU on reset issue

4. Action list Alex Action list Alex
Independent reset for each DLL for startup and reset
Independent low power mode for each DLL
Triplication of registers controlling DLL reset lines

5. Action list for the team
Decision between designs with 40 or 20 DLLs