1. Departamento Electrónica. Universidad de Alcalá. Madrid (Spain)
Response of the grid converters synchronization using p.u. magnitude in the control loop
Santiago Muyulema, Emilio J. Bueno, Francisco J. Rodríguez, Santiago Cóbreces, David Díaz
Departamento Electrónica. Universidad de Alcalá. Madrid (Spain)
Tlfno /6540 Fax
Abstract
Two sPLL systems are compared: in the first one, the error signal is Vdp (positive refence frame); whereas in the second one, the error signal is Vdp divided by its magnitude. For this reason, the method receives the name: “p.u. magnitude”. The desired objective is to reflect correctly the abrupt phase changes in the control synchronization system of the grid converters, which will be more important under hard unbalance dips and phase-angle jumps in the grid system.
Block diagram of grid converter
Block diagram of proposed synchronization method
udc
ua(t)
ea(t)
eb(t)
ec(t)
pulses
Cdc
uc(t) L1
ub(t)
uDC
meas.
PWM
generator
Current
control
Grid voltage DC
PLL
‘delay’
Filtro PI
VCO -1
DSC
Constant tuning
Experimental results
ωn=2π100
Conclusions
PLL proposed in this work has the next characteristics:
The constant tuning is independent of the grid voltage magnitude.
Eliminating the constant systematic error introduced when the error is multiplied by the magnitude.
In general, the response time under disturbances is faster and has a lesser overshoots.
It is useful in applications for motors drives because the voltages which are used have variable amplitude.
Acknowledgements
This work has been financed by the Spanish administration (MEC: ENE C04-01).
Dip type D 0.25pu.
PLL with input non normalized
PLL with input in p.u.
ISIE Vigo (Spain) 4-7 June 2007