1. Eiger characterization results
Roberto Dinapoli†, Anna Bergamaschi, Dominic Greiffenberg, Beat Henrich, Roland Horisberger, Ian Johnson, Aldo Mozzanica, Valeria Radicci, Bernd Schmitt, Xintian Shi.
Paul Scherrer Institut,
5232 Villigen PSI, CH.
†Corresponding author:
The pixel*
Abstract
Readout chip features
Pixel size
75 x 75 µm2
Gain
44.6 μV/e-
Peaking time
31 ns
Ret. to 1%
151 ns
Noise (simulated)
135 e-rms
Static power dissipation
8.8 μW/pixel
Transistor count
430/pixel
Pixel counter
configurable (4,8,12 bit mode), binary, double buffered for continuous readout
Threshold adjust
6 bit DAC/pixel
EIGER is the next generation single photon counting x-ray detector developed at Paul Scherrer Institut (PSI) for synchrotron based applications. It is a hybrid silicon pixel detector that features a 75x75 μm2 pixel size, a maximum frame rate capability of ~22 kHz (independent on the detector size), double buffered storage for continuous readout and a dead time between frames of ~3 μs. The chip is designed with Hardening By Design techniques to obtain high radiation tolerance from a commercial 0.25μm CMOS technology. An EIGER module is constructed from a ~4x8 cm2 monolithic sensor bump-bonded to 4x2 readout chips, thus resulting in a 0.5 Mpixel detector. Several modules can be tiled together to form large area detectors. Measurements performed up to now on several detector systems, going from single chip to full module, confirm that the module system can be used as building block for multi-module detectors. A 23x23cm2, 9 Mpixel detector is currently being developed.
The readout chip
Technological process
UMC 0.25 µm, CMOS
Power supplies
1.1 V (analog), 2 V (digital), 1.8 V (I/O)
Radiation tolerance
Radiation tolerant design (>4 Mrad)
Pixel array
256 x 256 = 65536
Chip size
19.3 x 20 mm2
Other features
Overflow control, XY-addressability and analog out for testing
The EIGER readout chip (in the picture) keeps the noise and speed performance of the previous chip of the Pilatus family (Pilatus II) and improves it in every other respect; in particular pixel size (reduced >5x), pixel count (>11x), double buffering, but most of all readout speed (>1000x for big detectors).
*Simulations done with “standard” settings. “Low noise” or “high speed” settings can improve performance for applications with specific needs.
From a single chip to a module
2cm
8 cm
2cm
Picture of a single chip test system used for all initial tests (top), and to take the image of a flower (right top). Tests done with this system proved that it is possible to achieve frame rates up to ~22 kHz in 4 bit mode (right bottom, frame from a movie showing a cpu fan with a hole in a blade, rotating at ~100Hz).
4 cm
8 cm
Picture of the half module test system and the corresponding module adapter board (top) used to take the image of an anchovy (bottom). Very high bump-bonding yield was achieved.
Picture of a full module system (left) used to take the image of a bird (right). Every module is composed by a monolithic detector bump-bonded to 8 frontend chips. It is served by two readout boards which perform data readout and formatting, local data storage on a memory and communication with the control system over 10 Gb Ethernet.
Single chip system characterization results
Towards multi-module systems
Two set of tests were performed both with lab x-ray sources and at the Swiss Light Source on single chip systems produced with chips coming from two different lots, the first one having foundry production faults. Results from the second lot only are presented.
Eiger
THRESHOLD CALIBRATION
Cl, 2.6keV!
Noise
Beamline
X-ray tube
E=20Kev
RATE CAPABILITIES
X-Ray energy (keV)
Measured threshold dispersion after trimming <30 e-
NOISE AND THRESHOLD DISPERSION
Gain: setting of the preamp feedback bias voltage. 9M
All tests performed up to now confirm that the module system can be used as building block for multi-module detectors. Several modules can be tiled to form big area detectors; the picture shows a first draft of the 23x23cm2, 9 million pixel detector (EIGER 9M) that we are currently developing for the cSAXS beamline at PSI.
Pixels are illuminated with x-rays and the measured pixel count rate is plotted versus the known incoming photon rate. The data are fitted with a a paralizable counter model and the  parameter which expresses the rate capability is calculated. Again, every line in the plot corresponds to a different preamp setting. In “high speed” mode the chip features  values < 128 ns.
The noise performance can be extracted from the slopes of the measured S-curves. The plot shows the noise performance as a function of the photon energy for different preamp settings. In “very low noise” mode the chip has a noise of ~100 e-. Threshold dispersions of <30 e- were also measured.
For every point in the plot an S-curve is measured and the threshold voltage extracted. The plot relates the comparator threshold voltage with the energy of the incoming photons. Every line in the plot corresponds to a different setting of the preamp feedback voltage (Gain). In “very low noise” mode the chip can reach thresholds < 3keV.