1. Memory Hierarchy Virtual Memory, Address Translation
Slides contents from:
Hennessy & Patterson, 5ed. Appendix B and Chapter 2.
David Wentzlaff, ELE 475 – Computer Architecture.
MJT, High Performance Computing, NPTEL.

2. Process/Program Address Space
Byte Address
CODE
Compiler assumes a linear address space
Byte 0 to Byte 232-1
Virtual Address space
The entire process data structure may not be present in MM at all times. .
DATA
HEAP
STACK
232-1

3. Paged Virtual Memory . . . Page Number 0 MAIN MEMORY
Virtual Address Space
MAIN MEMORY
Byte
Page Number 13
Virtual Page
Number 0
Physical
Address Space .
Virtual Page
Number 1
Page Number 1 .
Page Number 2 .
HARD DISK
Page Number N-1
Virtual Page
Number N-1
232-1

4. The Memory Hierarchy Physical Addresses Virtual Addresses Virtual

5. Address Translation Table
Physical Page Numbers
Virtual Address
VPN 0
PPN 0
VPN PO
VPN 1 .
PPN .
PPN PO
Physical Address
VPN N-1

6. Paged Virtual Memory
48 bit Virtual Addresses, 40 bit Physical Addresses. Page size = 16KB. How many entries in a process's Page Translation Table? What is the size of the Page Translation Table?

7. Virtual Memory

8. Address Translation Table
MAIN MEMORY
HARD DISK
Physical Page Numbers
Disk Addresses V
Virtual Address
VPN 0
VPN PO
VPN 1
PPN
Disk Address
PPN PO
Physical Address
VPN N

9. Implementation of Address Translation
Process always uses virtual addresses
Memory Management Unit (MMU): part of CPU; hardware that does address translation
The page tables are (at best) present in the MM (OS virtual address space)
One main memory reference per address translation!
To translate a virtual memory address, the MMU has to read the relevant page table entry out of memory
Caches recently used translations in a Translation Lookaside Buffer (Page Table Cache)

10. Caches and Address Translation
Physically Addressed Cache
Virtual
Address
Physical
Address
CPU
MMU
Cache
Main
Memory
Virtual
Address
Cache
Miss
Physical
Address
CPU
Cache
MMU
Virtually Addressed Cache

11. Which is less preferable?
Physical addressed cache
Hit time higher (cache access after translation)
Virtual addressed cache
Data/instruction of different processes with same virtual address in cache at the same time ...
Flush cache on context switch, or
Include Process id as part of each cache directory entry
Synonyms
Virtual addresses that translate to same physical address
More than one copy of a block in cache ...

12. Synonyms (Aliases) L2 uses virtual addresses
VA-T1
VA-T2 P1 t1 P2 t2
Shared L2
L2 uses virtual addresses
T1 and T2 share data from page X X
2 copies of one physical
page in the cache!

13. Virtually Indexed Physically Tagged Cache (VIPT)
Overlapped Operation
MMU
Virtual
Address
Tag check
using PA
Cache
CPU
Indexing
using VA
Virtually Indexed Physically Tagged Cache (VIPT)
Other options: PIPT, VIVT

14. Recall – Cache Access =? Direct mapped, 32 KB, 32B block,
32b main memory address
32 b address
Tag is not needed until the cache line
has been read
Tag
Index (10b) 3
Offset 2
W 1
32B Block W
W 8
To Processor
W 1 W
W 8 =?
. . . No
Cache Miss
Yes
Cache Hit

15. VM Example =? =? =? 64 b VM address Virtual Page No. (50)
Page Offset (14)
(43)
(7)
TLB Tag
TLB Index
Index (8)
Offset (6)
(26)
26b
Cache Block
Physical Address (Tag) =? =?
L1 Hit/Miss
TLB Hit/
Page Fault
Physical Address (40)
To L2
Tag
Index
Offset
L2 Cache Block
Index comes from the Virtual Address
(Virtually Indexed) =?
Tag comes from the Physical Address
(Physically tagged)

16. Fast Translation Address translation is on the critical path
Paging – 2 memory accesses!
Address Translation Table + Data
Translation Lookaside Buffer (TLB): Part of MMU that caches address translations

17. Page Fault
Virtual address generated by processor is not available in main memory
Detected on attempt to translate address
Page Table entry is invalid
Must be `handled’ by operating system
Identify slot in main memory to be used
Get page contents from disk
Update page table entry
Provide data to the processor

19. Size of a Page Page is the unit of Memory Management
Too large vs. Too small.
Page Offset field need not be translated
What if the Page Offset field was 12 bits? (Page size = 4KB)

20. Translation Lookaside Buffer
Cache of page table mappings
32 – 4096 entries long
SA, FA, or DM
Dirty flag – use during page write back
Ref – used for LRU
VPN
(tag)
PPN
(data)
Valid
Ref
Dirty
Access Rights