1. Topics Basic fabrication steps. Transistor structures.
Basic transistor behavior.
Latch up.

2. Fabrication processes
IC built on silicon substrate:
some structures diffused into substrate;
other structures built on top of substrate.
Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped)
Wires made of polycrystalline silicon (poly), multiple layers of aluminum/copper (metal).
Silicon dioxide (SiO2) is insulator.

3. Simple cross section SiO2 metal3 metal2 metal1 transistor via poly n+
substrate n+ p+
substrate

4. Photolithography
Mask patterns are put on wafer using photo-sensitive material:

5. Process steps
First place tubs to provide properly-doped substrate for n-type, p-type transistors:
p-tub
n-tub
substrate

6. Process steps, cont’d. Pattern polysilicon before diffusion regions:
gate oxide
poly
poly
p-tub
n-tub

7. Process steps, cont’d Add diffusions, performing self-masking: poly
p-tub n+ n+
n-tub p+ p+

8. Process steps, cont’d Start adding metal layers: metal 1 metal 1 vias
poly
poly
p-tub n+ n+
n-tub p+ p+

9. Level 2 metal Polish SiO2 before adding metal 2: metal 2 metal 1
vias
poly
poly
p-tub n+ n+
p-tub p+ p+

10. Transistor structure
n-type transistor:

11. Transistor layout
n-type (tubs may vary): L w

12. Drain current characteristics

13. Drain current Linear region (Vds < Vgs - Vt):
Id = k’ (W/L)(Vgs - Vt)(Vds Vds2)
Saturation region (Vds >= Vgs - Vt):
Id = 0.5k’ (W/L)(Vgs - Vt) 2

14. 90 nm transconductances Typical parameters: n-type: p-type:
kn’ = 13 A/V2
Vtn = 0.14 V
p-type:
kp’ = 7 A/V2
Vtp = V

15. Current through a transistor
Use 90 nm parameters. Let W/L = 3/2. Measure at boundary between linear and saturation regions.
Vgs = 0.25V:
Id = 0.5k’(W/L)(Vgs-Vt)2= 0.12 A
Vgs = 1V:
Id = 7.2 mA

16. Basic transistor parasitics
Gate to substrate, also gate to source/drain.
Source/drain capacitance, resistance.

17. Basic transistor parasitics, cont’d
Gate capacitance Cg. Determined by active area.
Source/drain overlap capacitances Cgs, Cgd. Determined by source/gate and drain/gate overlaps. Independent of transistor L.
Cgs = Col W
Gate/bulk overlap capacitance.

18. Latch-up CMOS ICs have parastic silicon-controlled rectifiers (SCRs).
When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip.
Early CMOS problem. Can be solved with proper circuit/layout structures.

19. Parasitic SCR
circuit
I-V behavior

20. Parasitic SCR structure

21. Solution to latch-up
Use tub ties to connect tub to power rail. Use enough to create low-voltage connection.