1. CS 286 Computer Organization and Architecture
Input/Output
and Bus
Department of Computer Science
Southern Illinois University Edwardsville
Fall, 2017
Dr. Hiroshi Fujinoki
I/O_1/001

2. CS 286 Computer Organization and Architecture
Methods to communicate I/O devices
I/O devices
Hardware sub-components in a computer system
Devices a CPU can send/receive data to/from
Connected to a CPU by bus (shared wires)
Each device is assigned a unique ID (I/O port address)
CPU 
HDD
Memory
FDD
Monitor  
Bus (shared wires)
Modem
Printer
Keyboard
Mouse 
I/O_1/002

3. CS 286 Computer Organization and Architecture
FROM
Memory
I/O Device TO
 Interrupt
Memory
I/O Device
 Polling
N.A.
 Centralized DMA
 ON-Card DMA
(“move” instruction)
 DMA
 Programmed I/O
 DMA
 Centralized DMA
 ON-Card DMA
 DMA = “Direct Memory Access”
I/O_1/003

4. CS 286 Computer Organization and Architecture
Methods to communicate I/O devices
Methods
Direction
Who do it?
 I/O device  Memory
The main processor
 Interrupt
 Memory  I/O device
The main processor
 Programmed-I/O
 Polling
 I/O device  Memory
The main processor
 Centralized-DMA
 I/O device  Memory
 Memory  I/O device
The shared central DMA
(on the motherboard)
 On-Card DMA
 I/O device  Memory
 Memory  I/O device
On-card DMA
“DMA” = “Direct Memory Access”
I/O_1/004

5. CS 286 Computer Organization and Architecture
Data Transmission for I/O devices
Interrupt: A mechanism
that notifies unpredictable
I/O events to a processor
(1) Data transfer by interrupt
= hardware interrupt + data transfer by CPU
 = Hardware Interrupt
for each byte received
+ = By CPU
CPU
BUS
Memory
 interrupt signal
 Device Read
 Data transfer to memory
To Network
Network
Interface
Card
Buffer
I/O_1/005

6. repeated multiple times
CS 286 Computer Organization and Architecture
Interrupt
These steps will be
repeated multiple times
Procedures 
 a packet arrives
 NIC generates interrupt signal
and send it to the CPU 
NIC
CPU
Memory
 CPU makes a context
switch  
 CPU reads data
 CPU starts processing
the packet 
 CPU writes data to
memory 
I/O_1/006

7. CS 286 Computer Organization and Architecture
(1) Data transfer by interrupt
(from an I/O device to MEMORY)
 A NIC receives one byte from network
 A NIC generates an interrupt signal to CPU
 CPU jumps to interrupt service routine (device driver) of this NIC
 CPU reads the received byte from the buffer of this NIC
 CPU writes this byte to the memory
 Repeats  through  as many as bytes in a packet
I/O_1/007

8. CS 286 Computer Organization and Architecture
Data Transmission for I/O devices
Programmed I/O: A mechanism
for a processor to send
out-going data to I/O devices
(1) Data transfer by programmed I/O
for each byte
 = Data read from memory by CPU
 = Data sent to an I/O device by a CPU
CPU
Memory
 Data transfer to I/O device
 Data transfer to CPU
BUS
Network
Interface
Card
To Network
I/O_1/008

9. CS 286 Computer Organization and Architecture
Data Transmission for I/O devices
(2) Data transfer by Direct Memory Access (DMA)
(A) By DMA controller on the system-board (“Centralized DMA”)
CPU
DMA
Controller
Memory
 Read status
 interrupt signal
 Command
BUS
To Network
Network
Interface
Card
Buffer
Cycle Stealing
I/O_1/009

10. CS 286 Computer Organization and Architecture
Data Transmission for I/O devices
(B) By DMA controller on a device controller board (“On-Card DMA”)
CPU
DMA
Controller
Memory
Signal the CPU
when done
BUS
Network
Interface
Card
Buffer
DMA
Controller
To Network
Burst mode
I/O_1/010

11. CS 286 Computer Organization and Architecture
(A) By DMA controller on the system-board (“Centralized DMA”)
(from an I/O device to MEMORY)
 A NIC receives one packet (not bytes) from network
 A NIC generates an interrupt signal to CPU
 CPU jumps to interrupt service routine (device driver) of this NIC
 CPU reads the information of this packet from this NIC register
 CPU sets DMA command, # of bytes received and memory address
 DMA controller starts transferring byte by byte from NIC buffer to
memory (cycle stealing)
I/O_1/011

12. CS 286 Computer Organization and Architecture
(B) By DMA controller on a device controller board (“On-Card DMA”)
(from an I/O device to MEMORY)
 A NIC receives one packet (not bytes) from network
 DMA controller on the NIC starts transferring byte by byte from the
buffer in the NIC to memory
I/O_1/012

13. CS 286 Computer Organization and Architecture
DMA
Procedures 
 A packet arrives
 NIC sends interrupt signal
to CPU 
NIC
CPU
Memory
 NIC transfer data to
memory (after all data arrives) 
 Context switch  
 CPU starts processing the
packet in main memory
I/O_1/013

14. CS 286 Computer Organization and Architecture

15. CS 286 Computer Organization and Architecture
Polling
Procedures 
 a packet arrives
 CPU makes a context
switch 
 CPU checks a register
in NIC 
NIC
CPU
Memory 
 CPU reads data 
 CPU starts processing
the packet
 CPU writes data to
memory 
I/O_1/015

16. CS 286 Computer Organization and Architecture
Performance Analysis
Interrupt
Polling
DMA
Response Time
Response Time = Waiting time after a packet arrives
CPU Utilization
CPU Utilization = Number of machine cycles
Buffer Size
Buffer Size = Size of buffer on a NIC
Cost
Cost = Cost of a NIC
I/O_1/016

17. CS 286 Computer Organization and Architecture
Data Transmission for I/O devices
OUTPUT: Memory
I/O Device
(2) Data transfer by Direct Memory Access (DMA)
(A) By DMA controller on the system-board (“Centralized DMA”)
CPU
DMA
Controller
Memory
 Data transfer to I/O device
 Command
 Data read from memory
BUS
To Network
Network
Interface
Card
Buffer
I/O_1/017

18. CS 286 Computer Organization and Architecture
Data Transmission for I/O devices
OUTPUT: Memory
I/O Device
(B) By DMA controller on a device controller board (“On-Card DMA”)
Memory
CPU
 Command
 Data transfer to I/O device
BUS
Network
Interface
Card
Buffer
DMA
Controller
To Network
Burst mode
I/O_1/018

19. CS 286 Computer Organization and Architecture
(A) By DMA controller on the system-board (“Centralized DMA”)
(from MEMORY to an I/O device)
 CPU sends a DMA command (for data Tx to I/O device) to the
DMA controller
- Destination device address (I/O port #)
- Number of bytes to be transferred
- Beginning memory address
 The DMA controller reads one byte from memory
 The DMA controller sends the one byte data to the I/O device
 The above two steps ( and ) are repeated as many bytes as in a packet
 Once all the bytes in a packet are copied to the buffer,
OS can issue a command “Disk Write”
I/O_1/019

20. CS 286 Computer Organization and Architecture
(1) Data transfer by Programmed I/O
(from MEMORY to an I/O device)
 CPU reads data from memory
 CPU sends the data to the buffer in NIC
 The above two steps are repeated as many bytes as in a packet
 Once all the bytes in a packet are copied to the buffer,
OS can issue a command “Disk Write”
I/O_1/020

21. CS 286 Computer Organization and Architecture
(B) By DMA controller on a device controller board (“On-Card DMA”)
(from MEMORY to an I/O device)
 CPU sends a DMA command (for data Tx to I/O device) to the
DMA controller on the device controller for the NIC
 The DMA controller reads one byte from memory
 The DMA controller sends the one byte data to the I/O device
 The above two steps ( and ) are repeated as many bytes as in a packet
 Once all the bytes in a packet are copied to the buffer,
OS can issue a command “Disk Write”
I/O_1/021

22. The three methods for the OS to receive arriving packets from a NIC
To a network
NIC
CPU
How can the OS
Copy a packet from
NIC to its main memory? ?
Memory
Buffer
Memory
End System
1. Receiving packets by interrupt
2. Receiving packets by device polling
3. Receiving packets by DMA
I/O_1/000

23. data transfer is required
Data Transmission for I/O devices
Most of data from I/O devices
First go (save) to memory
Then CPU uses the data from memory
I/O device-to-memory
data transfer is required
Methods for I/O device to memory data transfer
Input (receive data) from devices
Output (send data) to devices
 By interrupt
 By programmed I/O
 By device polling
 By Direct Memory Transfer (DMA)
 By Direct Memory Transfer (DMA)
I/O_1/000

24. Methods to communicate I/O devices
 Separate I/O address space
CPU
Memory
Memory Addressing Wires (Ax)
Bus
Data Wires (Dx)
I/O Devices Addressing Wires
(1) Specify memory address using “memory addressing wires”
(2) Send/receive data to/from the memory address (using “data wires”)
I/O_1/000

26. Methods to communicate I/O devices
 Separate I/O address space
 Memory-Mapped I/O
Memory address space and I/O address space are separated
Memory addressing wires an I/O addressing wires are separated
Different data access instructions for memory and I/O devices
A parts of memory address space are used for I/O address space
(no separation for memory and I/O addresses)
The same wires are used as addressing wires for both memory and
I/O devices
Same data access instructions for memory and I/O devices
I/O_1/000

27. Methods to communicate I/O devices
 Separate I/O address space
CPU
Memory
Memory Addressing Wires
Data Wires
HDD
Keyboard
Monitor
I/O Devices Addressing Wires
(1) Specify I/O device (port) address using “I/O addressing wires”
(2) Send/receive data to/from the specified I/O device using “data wires”
I/O_1/000

28. Methods to communicate I/O devices
 Memory-Mapped I/O
CPU
Memory
Memory Addressing Wires
HDD
Keyboard
Monitor
Data Wires
I/O devices are also
addressed by memory
address wires
(1) Specify memory address using “memory addressing wires”
(2) Send/receive data to/from the memory address
I/O_1/000

29. Methods to communicate I/O devices
 Memory-Mapped I/O
CPU
Memory
Memory Addressing Wires
HDD
Keyboard
Monitor
Data Wires
(1) Specify I/O device address using “memory addressing wires”
(2) Send/receive data using the data wires
I/O_1/000

30. Methods to communicate I/O devices
 Separate I/O address space
 Memory-Mapped I/O
Memory
Address
Space
Load/Save
Load/Save
Memory
Address
Space
CPU
CPU
I/O Device
Address
Space
I/O Device
Address
Space
HDD
HDD
Keyboard
IN/OUT
Keyboard
I/O_1/000

31. System Clock Architecture (i8080)
ISA
Bridge
HDD
Modem
Sound
Memory
CPU Core
CPU Clock (8 MHz)
Only one clock cycle rate
All components running
at the same clock rate
I/O_1/000

32. System Clock Architecture (i286, i386)
CPU Clock (25, 33 MHz)
ISA Bus Clock (8 MHz)
ISA
Bridge L2
HDD
Modem
Sound
Memory
CPU Core
L1 Cache
Slow and fast components
now separated
Two different clock cycle
rates in a system
I/O_1/000

33. System Clock Architecture (i486)
Bridge L2
Memory
CPU Core
L1 Cache
Modem
HDD
Local Bus
ISA
Sound
Printer
CPU Clock (33, 40, 50 MHz)
PCI Bus Clock (33 MHz)
ISA Bus Clock (8 MHz)
Disk I/O and memory
systems are now separated
Three clock rates in a system
Two bridges (North and South)
I/O_1/000

34. System Clock Architecture (i486, Pentium)
Bridge L2
Memory
CPU Core
L1 Cache
Modem
HDD
Local Bus
ISA
Sound
Printer
CPU Clock (200 MHz)
System Bus Clock (33 MHz)
ISA Bus Clock (8 MHz)
Front Bus Clock (66 MHz)
CPU clock is now separated
Four different clock rates
in a system
I/O_1/000

35. System Clock Architecture (Pentium II and after)
Bridge L2
Memory
CPU Core
L1 Cache
Modem
HDD
Local Bus
ISA
Sound
Printer
L1 Clock (200 MHz)
System Bus Clock (33 MHz)
ISA Bus Clock (8 MHz)
Front Bus Clock (66 MHz)
CPU Clock (400 MHz)
CPU core is now separated
from L1 cache unit
Five different clock rates
in a system
I/O_1/000

36. User-Level I/O software
I/O Software Layers
User-Level I/O software
Device-independent OS software
Device Drivers
Interrupt Handler
Hardware (Device)
I/O_1/000

37. Details of I/O device access Command registers
Device registers
Details of I/O device access
Command registers
Parameter registers
Status registers
CPU
Data Wires
Device Controller
Command register
Device registers
Buffer
Parameter register
Example
Disk write
Status register
Success/Failure
Disk-Drive Unit (Device)
I/O_1/000