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Clock Driver PSpice Simulations IUCAA Bhushan Joshi Kalpesh Chillal

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Presentation on theme: "Clock Driver PSpice Simulations IUCAA Bhushan Joshi Kalpesh Chillal"— Presentation transcript:

1 Clock Driver PSpice Simulations IUCAA Bhushan Joshi Kalpesh Chillal
Pravin Chordia IUCAA

2 In-the-loop Compensated Clock Driver
Without Transmission line

3 In-the-loop Compensated Clock Driver Transient Analysis
Without Transmission line Transient Analysis

4 In-the-loop Compensated Clock Driver AC Analysis
Without Transmission line AC Analysis

5 In-the-loop Compensated Clock Driver PSpice Simulations
With Transmission line PSpice Simulations

6 In-the-loop Compensated Clock Driver
With Transmission line

7 In-the-loop Compensated Clock Driver Transient Analysis
With Transmission line Transient Analysis

8 In-the-loop Compensated Clock Driver AC Analysis
With Transmission line AC Analysis

9 Result of Compensated Clock Driver Implemented on test board
With Transmission line Transient Analysis (DSO screenshot)

10 Lead Compensated Clock Driver PSpice Simulations
With Transmission line PSpice Simulations Reference(1): Chapter 7,Voltage-Feedback Op Amp Compensation Literature Number SLOA079 Excerpted from Op Amps for Everyone Literature Number: SLOD006A Author : Texas Instruments Page: Reference(2): For Calculation of value of capacitor C22

11 Lead Compensated Clock Driver
With Transmission line Since Simulator can not take 0Ω and to keep same schematic 0.1Ω resistor is used

12 Lead Compensated Clock Driver Transient Analysis
With Transmission line Transient Analysis

13 Lead Compensated Clock Driver AC Analysis
With Transmission line AC Analysis

14 Lead Compensated Clock Driver Implementation on test board
With Transmission line Implementation on test board

15 Clock Driver without any Compensation
Load Cap

16 Result of Clock Driver without any Compensation

17 Clock Driver with Lead Compensation
Changed values Load Cap

18 Result of Clock Driver with Lead Compensation

19 Clock Driver with In-the-loop Compensation (Optimized R3,C2 values are selected for 680pF capacitor and transmission line as Load)

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22 OPA4140 Bipolar Bias PSpice Simulations

23 OPA4140 Bipolar Bias With 50pF capacitor and transmission line as Load
BW = 15 MHz PM = 68⁰

24 OPA4140 Bipolar Bias DC Sweep Analysis

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26 OPA4140 Bipolar Bias With 200pF capacitor and transmission line as Load Instable

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28 OPA4140 Bipolar Bias With 200pF capacitive load and NO transmission line 50Ω Series resistor as suggested in datasheet BW = 8 MHz PM = 45⁰ stable

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30 OPA4140 Bipolar Bias With 200pF capacitor and transmission line as Load 150Ω Series resistor BW = 5 MHz PM = 33⁰ stable Other compensation circuits to be tried

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