1. The Register File and ALU
CS/COE 0447 (term 2181)
Jarrett Billingsley

2. Class announcements
Today/Tuesday's lectures will be helpful for the project
Who's not gonna be here Tuesday? :^)
Since there was no lab last week…
This week's lab will be the size of/count for two labs.
It's due Thursday 11/30 by 11:59PM (two weeks)
Charge your laptops and do it in the car/bus/plane lol
EC assignment will definitely be out before break as well
Only 3 lectures of new material after break, then review
Final will be cumulative!
11/16/2017
CS/COE 0447 term 2181

3. How the display unit works now4 5 C D 8 3 2 4 5 8 3 4 5 C D 8 3 2
put r1, 0
Next High Byte
This way we can show a 16-bit number in an instant instead of the display changing while we write to it.
put r2, 1
Displayed Value (1 or 2 registers)
11/16/2017
CS/COE 0447 term 2181

4. A few more tips… 00 Do NOT use the registers' 0 input.
If you clear the display unit's registers using the 0 input, a put followed by a clr would never show the value.
This is because the 0 input is asynchronous: it doesn't care about the clock.
The description says: If Write Enable = 1 AND Clear = 1, on the rising edge of the Clock all registers should be set to 0.
The upper 7 bits of the immediate input are ignored.
We're just using the lowest bit to change the behavior.
To change the display components' background color, set the alpha to 255 as well. (0 means transparent.) 00 D Q WE
11/16/2017
CS/COE 0447 term 2181

5. The Register Files
11/16/2017
CS/COE 0447 term 2181

6. Register File The MIPS register file
In the instruction add t0, t1, t2, how many registers are read?
How many are written?
How many different registers are accessed?
There's one input or write port.
Register File
There are two output or read ports.
Each port can read a different register.
It needs a clock signal. What other control signals does it need? WE rd rs rt
How about a write enable?
And inputs to select the registers?
11/16/2017
CS/COE 0447 term 2181

7. It doesn't have to be this way
CISC CPUs usually have small sets of registers, and many have special purposes or behaviors.
RISC CPUs usually have 32* mostly-interchangeable registers: MIPS, RISC, SPARC, ARMv8, AVR, RISC-V…
8086 ax bx cx dx si di sp bp
z80 a f b c d e h l ix iy sp
6502 A X Y
PDP8 AC r0 r1 r2 r3 r4 r5 r6 r7 r8 r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
32/64 bits
12 bits
8 bits
Why is this? Well, what do you remember about the differences between RISC and CISC?
16 bits
11/16/2017
CS/COE 0447 term 2181
*Or 32 at a time

8. Tug-of-war
Register file design is constrained by several design requirements.
Compilers love lots of identical registers!
ISA says instructions have 2 operands and 1 destination.
…but there are diminishing returns.
Fast L1 cache? Not as many regs needed.
…except for this one instruction that has 2 destinations. D Q
Multi-issue CPU: need to read 4 regs and write 2.
…but context switches are slower.
Humans like intuitive assembly language!
With lots of registers, function calls are faster!
More registers means more silicon…
11/16/2017
CS/COE 0447 term 2181

9. A word of advice You will see many imperfect designs in your life.
But in engineering, perfection isn't always the goal.
Everyone has to work within the constraints they're given.
And if everyone does something the same way…
There are probably problems/constraints you don't know about.
Don't waste your time reinventing the wheel.
Find out why it's done that way first.
When it comes to register files, 32 registers is just a nice number. Not too many, not too few, a nice middle-ground.
Also don't be a judgmental ass about someone else's design because one, it's shitty, and two, they know more about why it was designed that way, so you're just being presumptuous
11/16/2017
CS/COE 0447 term 2181

10. Reading from one register
You have two registers, and you want to choose one to read.
What kind of component chooses? 83 D Q WE A 29 83 29 D Q WE
Reading from a register is technically combinational. B 1
A read port is made of a select signal, a MUX, and a data output.
11/16/2017
CS/COE 0447 term 2181

11. Writing
For the write port, we only want to write to one register at a time.
We'll have a select signal again…
When should we write to A? 83 D Q WE
Do we ALWAYS write to a register? How about in
beq A, 3, top?
select = 0 A
WE = 1
When should we write to B? 29 D Q WE
select = 1 B
WE = 1
11/16/2017
CS/COE 0447 term 2181

12. Only the register with WE=1 will store the data.
Close the door
When a register's write enable is 0, what happens to the data?
We can hook up the data input to all registers at once.
Data 83 D Q WE A
Only the register with WE=1 will store the data. 29 D Q WE B
11/16/2017
CS/COE 0447 term 2181

13. Chekhov's Gun
There's a component we haven't seen in a while which only sends an input value to one of its outputs. 83 D Q WE A WE WE 29 D Q WE 1 B WE
A write port is made of a select signal, a data input, a write enable, and some kinda logic to send the write enable to one register.
11/16/2017
CS/COE 0447 term 2181

14. The ALU

15. Arithmetic and Logic Unit
An ALU does all the stuff we talked about in the previous unit.
Remember lab 4?
This is a very simple ALU: it takes two 4-bit values, and either adds or subtracts them, based on a control signal.
11/16/2017
CS/COE 0447 term 2181

16. It really is that straightforward
An ALU can be entirely made of combinational logic. A + B -
The Op(eration) signal controls what the ALU does. Op
Again: do everything, but only pick the thing you need.
11/16/2017
CS/COE 0447 term 2181

17. Save Our Silicon An ALU can be a pretty sizeable chunk of space.
You might reuse the ALU hardware for multiple purposes. t2 t5
t2 & t5
and t0, t2, t5 t0
t0 - 0
bne t0, 0, lab1 PC 24
PC + 24
b lab2
But we can't do all three at the same time. (Structural Hazard!)
So either duplicate parts of the ALU, or use multi-cycle.
11/16/2017
CS/COE 0447 term 2181

18. Bit slicing The book makes the ALU like this.
This approach is called bit slicing: build a 1-bit ALU, then copy-and-paste it.
Then they make it more confusing???
It might be what they really use when designing a chip, but it's not great for learning.
It does the same thing but is way harder to understand.
11/16/2017
CS/COE 0447 term 2181

19. What about multiply and divide though??
MIPS also does them separately because they're slow.
mult t0, t1
add t2, t3, t4
and t2, t2, a2
...
move v0, t2
mflo v1
Main ALU
Then we run other stuff…
It sends the multiplication off to a separate unit. +- D Q
ctrl
×÷ Unit
…and later, ask for the result.
11/16/2017
CS/COE 0447 term 2181

20. Hey, that's neat actually
By making the multiply/divide unit separate from the rest of the CPU, we can do fun things like overclock it.
Maybe the CPU runs at 2 GHz, but the divider at 8 GHz.
Now the divider does 4 steps on each main CPU cycle.
Combine this with a fast predictive divider that computes 4 bits of quotient every cycle…
And now you have a divider that can do a 32÷32-bit division in only 2 CPU cycles in the best case!
But…
What should happen if the program tries to get the quotient before the division is done?
How do we "pause" the CPU when that happens?
These issues are (mostly) solved by superscalar execution.
11/16/2017
CS/COE 0447 term 2181

21. Ah, whatever, use as much silicon as you want
A multi-issue CPU can run multiple instructions in parallel.
And 2 ALUs, of course.
add t0, t0, a0
sub t1, t1, a1
These are two independent calculations. Let's do them at the same time! t0
Register File
ALU 1 a0
Now we need four read ports and two write ports. t1
ALU 2 a1
11/16/2017
CS/COE 0447 term 2181