1. Transistor Design Considerations for Power Amplifier Applications
Peter J. Zampardi, Juntao Hu, Cristian Cismaru, and Vijay Vijayakumar

2. Subtitle – Arial Narrow Bold 24pt
Outline
Introduction
Transistor Geometries
Device Size Limitations
Performance Limitations (from Geometries)
Device Level Thermal Considerations
Summary
Subtitle – Arial Narrow Bold 24pt

3. For Design, One Size Does Not Fit All!
Have Read A Lot of Papers Saying only 1 Transistor Style is Needed for PA
This is NOT TRUE!
This Talk Should Provide Food For Thought That Many Devices Can Be Useful
Depending on the Application

4. Device Performance vs. Application Measured RF Gain vs. Cbc/Ae
Monotonic at 900 MHz
Vce=3.5
Falls off a 5.8 GHz
(due to stability)
This changes with bias (I and V)
One Size Does Not Fit All

5. Only Practically Supportable with Scalable Model
Geometry Types
Straight Finger
Round Devices
Nb>Ne
Ne>Nb
Ne=Nb
Horseshoe
Ring
Dot
CBE
CEB
(BEBEBEBEB)
(EBE)
(EBEBEBE)
(½E)BEBEB(½E)
Device
Description
QSM
M1+BC base finger
M1 only on emitter connection
QSB
BC base finger (extra Cbc)
Narrower BC=lower Cbc
M1/M2 on emitter
QSB_ALT
1 Base, 2 Emitter version of QSB
QSF
1 Base, 2 Emitter
M1/M2 on emitter (at certain width) QS
1B, 1E, 1C, M1 only on E QR
True-ring emitter HBT
QRH
Horse-shoe (ring) emitter HBT QD
Dot emitter HBT
QSM
QSB
QSF QS
Only Practically Supportable with Scalable Model

6. Reliability Based Device Size Limitations How Big Can That Device Be?
ASSUMPTIONS:
Emitter limited current density or base limited current density (by your device reliability guy). Can be f(T, Vce)
Assume Two Metals with Limits: Jmax,m1, Jmax,m2
Ignore thermal considerations for now (We cover later)
First, we will evaluate the maximum emitter length that can be supported for a given emitter width.
WE=emitter width, LE=emitter length, JE,Max is maximum emitter current density (mA/mm2)
Since the wiring into the device will be through some amount of metal, then we have another limit due to the metallization:
WM=Metal connection width, JMetal,Max=maximum current for metal (mA/um)
To find the maximum value of emitter length (for simplification, we are considering a straight finger) we set these two equations equal to one another:
Metals Can Limit Emitter Width
Almost Independent of We

7. Not a Huge Problem for GaAs
DC/RF Emitter Utilization Factors
with
After: J. T. C. Chen, et al, “Bipolar microwave linear power transistor design,” IEEE MTT, vol. 27, no. 5, pp , 1979
Courtesy Peider Tseng
RF May Limit Devices
Not a Huge Problem for GaAs

8. Horseshoe - Size Limitations
Devices with Single Contacts, or
Non-uniformities Have Scaling Limits

9. Straight Finger Devices
Several Different Configurations
*Single Fingers: CBE, CEB (Ne=Nb), CBEB, CBEBC
Dual Fingers: CBEBEBC, CEBEC (for lower Cbc)
Four Fingers: CBEBEBEBEB
Nb>Ne Good For Low Noise
Can Be Wide (smaller array layout)
Not As Good for Cbc
*Some “Odd” Devices
CEBEBEC, C(1/2E)BEB(1/2E)C, etc
Better For Cbc
Okay for Rb
Width Limit on Outer Fingers
*Can only be fabricated in
Non-self aligned technology
Electrically, Straight Finger Devices
Are Very Versatile

10. Standard Straight Finger Devices
No Tab
Tab
SBE
WBC E B E
Important Design Rules
WBC (current handling)
SBE “Ledge Length” (reliability)
E2BP Spacing (reliability)
BC2BP Spacing We Le
Two Sides is Better
Than 1
For > 2 contacts, the equations become much messier
(see for example Rein and Schroter, SSE, V.34, No. 3, pp , 1991)
or T. Hook, SSE, Vol. 33, No. 10, pp , 1990
Design Rules Can Determine Which Device is Better
To Minimize Cbc There is a Crossover Point

11. Electrically, This is Actually Okay
T Transistor Layout
(already used WE,outer=1/2 WE,center)
We,outer=(1/2)*We,center
We,outer it your min We
Since Ic,outer=1/2 Ic,center
Vbe drop is the same for inner and outer fingers since current in outer fingers
is ½ because of area. Could be modeled with two-transistor model.
Electrically, This is Actually Okay

12. True-Ring Transistor (Scalable)
SC=Small Contact
Full Rings are Scalable
Performance is Good

13. RF Performance Metrics
Straight Fingers are Better for Base Resistance

14. Thermal Resistance Considerations
Device Level Rth Generally Proportional to BC Area
Improving Cbc usually fights with lowering Rth
Array Level is Function of LOTS of Stuff
Better to Be Uniform that Cool!
Abc For Device, Array Area For Array

15. Temperature Considerations
Piling More Metal on Devices is Good!
“Horseshoe”
M1 Only M1
Only M1
Only
“Horseshoe”
M2 + Shunt

16. We Use Rings, Ne+1, and Horseshoes In Products
Summary
Don’t Get Cheated By Your Device Design Team!
Different Devices Can Be Used to Optimize Different Performance Metrics
Minimum Cbc – use ring style transistors
Minimum Rb – use multifinger (Nb>Ne) HBT (best noise figure)
Thermal – spread the heat source out, lots of metal on device
Smallest Layout Area – biggest cell
Type Rb
Cbc
Thermal
Scaling
Ne+1 + -
Ne-1
Ring
Horseshoe
We Use Rings, Ne+1, and Horseshoes In Products

17. Increasing Cbc
Increasing Rb