1. Next steps – with notes from during the meeting 17 March 2016
J. J. John
with input from many colleagues

2. The work ahead List of main tasks:
Basic infrastructure / getting started
Phase 1 – on Nexys Video
Adapt the ABC130* star HDL code to the ABCN’
Adapt ITSDAQ firmware and software to read out the ABCN’
Creating a CHESS-2 data emulator
Phase 3 – on HSIO-2 with CHESS-2 daughterboard
Port the ABCN’ to the HSIO-2
Commission/debug with CHESS-2
Phase 4 – on CMOS demonstrator module
Help specify the CMOS demonstrator module (FPGA aspects)
Port the ABCN’ to the FPGAs on the hybrid/PCB
Commission/debug ABCN’ running on the module
This made sense to those attending.
+ Phase 2 – running ABCN’ on one FPGA board and the DAQ on a 2nd FPGA board
+ merge in finalised ABC130* interface (L0tag etc)

3. Basic infrastructure - 1
Hardware, source code and repository
Divided up these tasks during meeting.
Task
Who
Obtain Nexys Video board, -- Oxford has one, thanks to Peter and Bruce for the loan.
Test with current ITSDAQ firmware and software
After discussion: it is some work to get communications set up to a Nexys Video with ITSDAQ, so allow some time for this. The steps are:
need a PC with a second network interface – extra card or USB network interface
programme the ITSDAQ firmware for Nexys V into the EEPROM onboard
talk to it via the ITSDAQ software (get from SVN, compile with ROOT)
WireShark is useful for monitoring network activity
There is a pushbutton to send a packet out of the Nexys V to the PC
It would be useful if we could write a register to gain control of the LEDs, then write another register to set the LEDs (sanity check/reasssurance)
All sites
Set up repository for ABCN’ with current ABC130* code
After discussion: decided on Gitlab at CERN
Wojtek

4. Basic infrastructure - 2
ABC130* learning/reference materials
Task
Who
Update ABC130* block diagram with bit widths (buses, memories)
Jaya John
Prepare or generate diagram of ABC130* codebase
Matt
Understand current version of ABC130* serial interface – triggers and commands  decide the way forward on the serial interface
After discussion, we think we could use two possible interfaces from ITSDAQ to the ABCN’, in the time before the ABC130*-HCC* interface is finalised (L0tag etc)
re-use ABC130 serial interface (L0/Cmd and R3/L1) – we get blocks for free, including in the ITSDAQ firmware and software, and the “TMU” block to control the CHESS-2 Data Emulator. (TMU = Trouble Making Unit, a block which acts like a separately-addressable chip on the L0/CMD bus)
register read/write interface – which is what the commands resolve
Wojtek (with help from Matt and Jaya John)

5. Phase 1 – on Nexys Video Task Who Create a CHESS-2 data emulator (DEM)
Generate random hits on emulated strips
Process hits as CHESS-2 does, to output data in same format
Provide a control interface to DEM. It should look like one of the * series of chips – receive commands on the same serial line from the DAQ firmware.
We agreed to revisit who will do what, when we are further with the basics.
Adapt the ABC130* star HDL code to the ABCN’
Adapt widths of FIFOs/memories
Look at intention of Cluster Finder, see what is applicable
Provide a * Command-to-SACI bridge, to control AMS-CHESS-2
Provide a * Command-to-SPI bridge, to control TJ-CHESS-2
Adapt ITSDAQ firmware and software to read out the ABCN’
Need to use current serial line protocols as working in the present ABC130* code see discussion though at the bottom of slide 4

6. Phase 1 ABCN’ tasks in more detail – 1
Data Path
Organize Chess 2 data into pipeline memory
L0 selection into Event Buffer
R3/L1 (PR/LP) selection into packetizer
Build 54-bit packets with 33-bit payloads
Design this structure early!
Port ABC130 serializer
-- from Paul Keener’s slides of 11 Feb
While these refer to the ABC130, the big picture of the work is still the same.

7. Phase 1 ABCN’ tasks in more detail – 2
Command Protocol Convertor
Port ABC130 Command Decoder & Registers
Registers can be simplified (don’t need triplication)
Interface to outgoing command structure
Design readback mechanism
-- from Paul Keener’s slides of 11 Feb