1. Thin Planar Sensors for Future High-Luminosity-LHC Upgrades
Tobias Wittig, Alexander Lawerenz, Ralf Röder

2. Thin planar sensors at CiS Status of active edges processed at CiS
Contents
Thin planar sensors at CiS
Status of active edges processed at CiS

3. Motivation for thin planar sensors
Target thickness: 150 µm µm
Comparison to sensors with standard thickness:
lower material budget
lower depletion voltage
higher collected charge
higher radiation hardness
(S. Terzo et al., arXiv: v2 (2014))

4. Thin planar sensors at CiS
Design in collaboration with Max-Planck-Institut für Physik (MPP, in Munich) and CiS
slope
~ 300 µm (thickness 100 µm)
265 µm (thickness 150 µm)
frame
~ 400 µm
membrane
guard ring structure within the thinned area

5. Sensor thinning by KOH etching
Prototype run with MPP
n-in-p ATLAS pixel sensors
FE-I4 Quad-Sensors (41 x 36 mm²)
FE-I4 SCS
Starting thickness 525 µm, target thicknesses 150/100 µm
Dummy wafer trials showed proof of principle for large area cavity etching
Advantage of this approach:
No support wafer needed
Enhanced stabilty after thinning due to the remaining frames
Simple thinning (only wet chemichally)
It works on {100} wafers

6. Sensor thinning by KOH etching - dummies

7. Sensor thinning by KOH etching – sensor run
One batch of 25 wafers processed (two different target thicknesses (150 µm and 100 µm)
No mechanical breakage
Homogeneity of the membranes:
large scale (thickness measurements)
same homogeneity as seen for the dummy wafers
thickness fluctuations in the order of 5…10 µm could be maintained
small scale (AFM measurements)
looks more than satisfying
average fluctuations in the order of a few 10 nm

8. Sensor thinning by KOH etching – sensor run
One batch of 25 wafers processed (two different target thicknesses (150 µm and 100 µm)
No mechanical breakage
Homogeneity of the membranes:
large scale (thickness measurements)
same homogeneity as seen for the dummy wafers
thickness fluctuations in the order of 5…10 µm could be maintained
small scale (AFM measurements)
looks more than satisfying
average fluctuations in the order of a few 10 nm

9. Sensor thinning by KOH etching – sensor run
One batch of 25 wafers processed (two different target thicknesses (150 µm and 100 µm)
No mechanical breakage
Homogeneity of the membranes:
large scale (thickness measurements)
same homogeneity as seen for the dummy wafers
thickness fluctuations in the order of 5…10 µm could be maintained
small scale (AFM measurements)
looks more than satisfying
average fluctuations in the order of a few 10 nm

10. Sensor thinning by KOH etching – sensor run
One batch of 25 wafers processed (two different target thicknesses (150 µm and 100 µm)
No mechanical breakage
Homogeneity of the membranes:
large scale (thickness measurements)
same homogeneity as seen for the dummy wafers
thickness fluctuations in the order of 5…10 µm could be maintained
small scale (AFM measurements)
looks more than satisfying
average fluctuations in the order of a few 10 nm

11. Sensor thinning by KOH etching – sensor run
Shear stress (unit DU)
Shear stress (membrane thickness 100 µm)
Shear stress (membrane thickness 150 µm)
Shear stress is measured by the polarisation state of a reflected (linearly polarised) laser beam
Shear stress for different thicknesses are similar

12. Sensor thinning by KOH etching – sensor run
Slopes are doped lower than the membrane itself due to the tilted angle between the slopes and the penetrating ion beam.
SIMS depth profiles on the membrane and the four slopes

13. Sensor thinning by KOH etching – sensor run
Electrical characterisation
depletion voltages as expected
~ 15 V for 150 µm membrane
~ 7 V for 100 µm membrane
> 200 V unthinned
Characteristics of thinned and not-thinned diodes

14. Sensor thinning by KOH etching – sensor run
Electrical characterisation
depletion voltages as expected
~ 15 V for 150 µm membrane
~ 7 V for 100 µm membrane
> 200 V unthinned
IV characteristics look very well
breakdown voltages mostly > 50 V above Vdepl
Electrical yield of pixel sensors:
150 µm
100 µm
total
FE-I4 Quads
88 %
64 %
76 %
FE-I4 SCS
98 %
89 %
94 %
IV characteristics of one wafer thinned to 150 µm

15. Under bump metallisation (UBM) and assembly
Mask-based electroless Ni-UBM and Pt-UBM
Done for CMS pixel production, in combination with In-bumps
Relatively thin film on sensor surface (several 100 nm)
Dicing within the thinned areas
Successful bump-bonding and flip-chipping at IZM
FhG IZM
UBM (TiNiAu)

16. Under bump metallisation (UBM) and assembly
Mask-based electroless Ni-UBM and Pt-UBM
Done for CMS-pixel production, in combination with In-bumps
Relatively thin film on sensor surface (several 100 nm)
Dicing within the thinned areas
Successful bump-bonding and flip-chipping at IZM
Source scan of FE-I4 single chip assembly (by coutesy of A. Macchiolo, MPP)

17. Summary of results on KOH thinned sensors
Electrical yield: SCS: 76 %, QS: 94 % (before UBM and dicing),
Electrical yield for the UBM: 98 %,
Mechanical yield for the dicing step: 88 %,
Electrical yield for the dicing step: 100 %.

18. Multi project wafer (MPW) prototype wafer run
Analog technology as MPP run (+Poly-Si)
n-in-p, backside cavity etching
Less ambitious as cavity areas are much smaller. But: on some wafers thinner membranes (see below)
Several different sensors on wafer
micro strips (80 µm pitch, Poly-Si- Resistors)
diodes (different kinds)
Two kinds of wafer material with various resistivities
Epi (525 µm substrate + 50 µm Epi)
etching the complete substrate
FZ (285 µm) and MCz (300 µm)
etching to 50, 100, 150, 200 µm (+unetched)

19. Multi project wafer (MPW) prototype wafer run
IV characteristics of one wafer with areas of two thicknesses (original thickness and 50 µm thickness)

20. Current work
On the way: Processing of 6 inch dummies with two different layouts (membrane sizes)
slope
~ 400 µm (thickness 100 µm)
370 µm (thickness 150 µm)
frame
~ 320 µm
membrane

21. Current work
On the way: Processing of 6 inch dummies with two different layouts (membrane sizes)
slope
~ 400 µm (thickness 100 µm)
370 µm (thickness 150 µm)
frame
~ 320 µm
membrane

22. Active edges at CiS

23. Active edges at CiS
Reduction of inactive sensor edge by doping of side walls
Several parameters are varied which can be compared:
p- and n-type bulk
sensor thickness (300 & 100 µm)
three methods of doping the side walls
numerous edge designs had been simulated
most promising ones were implemented in the layout
Variations also include:
trench width: µm
de: µm
dBR: µm

24. Active edges at CiS Present status: doping of the side walls finished
Currently finishing the last layers (very challenging due to the 3D structured surface)
Soon coming: Measurements of the electrical performance
Light microscopy
etched trench
bias / guard ring
pixel
250 µm

25. Active edges at CiS Present status: doping of the side walls finished
Currently finishing the last layers (very challenging due to the 3D structured surface)
Soon coming: Measurements of the electrical performance
125 µm

26. Summary & acknowledgements
Our approach of thinning planar sensors is based on a masked KOH etching, where the area outside the sensor remains unteched.
This KOH membrane etching is suitable for thinning different kinds of sensors (down to 50 µm thickness).
Active Edges activities still on the way at CiS, but mechanical treatment (etching of the trenches) fulfilled.
This project is funded by the German Federal Ministry of Economics and Technology (BMWi), project “LAT”, MF and project “Active Edges”, MF

27. Contact CiS Forschungsinstitut für Mikrosensorik GmbH
Konrad-Zuse-Straße 14 Alexander Lawerenz
99099 Erfurt Head of Silicon Detector Department
Germany phone: