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Intel Validation of TGn Simulation Scenarios
January 2002 doc.: IEEE /xxxr0 November 2003 Intel Validation of TGn Simulation Scenarios Adrian P Stephens Dmitry Akhmetov Sergey Shtin Intel Corporation Adrian Stephens, Intel John Doe, His Company
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January 2002 doc.: IEEE /xxxr0 November 2003 Purpose of the work To show that the simulation scenarios defined in can be implemented in a realistic protocol To encourage a “yes” vote to the following: Move to adopt the simulation scenarios in r<xx> Adrian Stephens, Intel John Doe, His Company
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Simulation Methodology
November 2003 Simulation Methodology Adrian Stephens, Intel
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November 2003 Model & Features Framework: Opnet V9 with substantially modified components PHY Model: TGn channel models (with shadowing) Collect SNIR per sub-carrier per interference region Adaptive Bit Loading MAC Model: DCF channel access RTS/CTS training exchange Aggregate transmission using ABL-trained packets Adrian Stephens, Intel
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Implementation of scenarios
November 2003 Implementation of scenarios Only interested in the QoS (UDP) flows Don’t have EDCA or HCCA yet Assume HCCA good enough to isolate UDP based on polled TXOPs from loss of service by applied TCP/IP flows Measure throughput, delay, number of packets lost and delayed “too long” Adrian Stephens, Intel
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PHY Mode 1x1 Antenna configuration Channel width 80MHz
November 2003 PHY Mode 1x1 Antenna configuration Channel width 80MHz to give 4x raw speed Because we haven’t completed our MIMO model yet Expect to be similar to 2x2 40MHz results ABL operation during data transmissions Adrian Stephens, Intel
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MAC Parameters RTS/CTS/Burst/Block Ack protocol
November 2003 MAC Parameters RTS/CTS/Burst/Block Ack protocol MIN Burst Size = 3 MPDU MAX Burst Size = 31 MPDU TXOP limit = 2 microseconds Full TXOP usage (Always try and fill TXOP) Adrian Stephens, Intel
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November 2003 Status of results Initial simulation results show that all the simulated scenarios meet the application QoS requirements except #2, 6, 9, 11. Have not implemented 9 & 11 Don’t expect any problems with 9 & 11 Simulations #2 & 6 Need EDCA (which we don’t have yet) to give priority to VoIP over video. Using DCF means high Video Rate traffic causes UDP voice to exceed its delay limits Adrian Stephens, Intel
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November 2003 Conclusion All scenarios except 2,6, 9 and 11 have been simulated as specified including only UDP traffic It is reasonable to expect that all scenarios will meet the QoS limits within our model when EDCA is implemented Recommend we recommend acceptance of these scenarios to TGn in Albuquerque Any changed models/scenarios will need re-validation Adrian Stephens, Intel
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QoS Performance for SS #1
November 2003 QoS Performance for SS #1 Scenario #1 RX TX Maximum delay ms Peak ETE delay Total received PLR (too late) STA0 STA7 30 1900 0.63% STA8 1901 0.47% STA9 1902 STA10 STA11 16 12455 0.16% PLR of the rest STAs is 0 (zero) Adrian Stephens, Intel
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QoS Performance for SS # 4
November 2003 QoS Performance for SS # 4 Scenario #4 RX TX Maximum delay ms Peak ETE delay Total received % of “too late” STA0 STA28 30 1876 0.23% PLR of the rest STAs is 0 (zero) Adrian Stephens, Intel
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QoS Performance for SS # 4
November 2003 QoS Performance for SS # 4 Scenario #4 RX TX Lost Packets Total Rx % PLR STA0 STA1 13 4981 0.26 STA2 3 4960 0.06 STA3 2 4958 0.04 STA6 1884 0.15 STA7 7 2421 0.28 STA8 5 2410 0.21 STA25 1895 0.36 STA26 11 1875 0.58 STA27 1896 0.11 STA28 20 1876 1.06 Adrian Stephens, Intel
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Detailed Results for SS # 1
November 2003 Detailed Results for SS # 1 Adrian Stephens, Intel
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November 2003 Aggregate Throughput Adrian Stephens, Intel
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November 2003 STA0 Rx Rate Adrian Stephens, Intel
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November 2003 STA0 Tx Burst Size Adrian Stephens, Intel
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STA0 Medium Access Delay
November 2003 STA0 Medium Access Delay Adrian Stephens, Intel
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STA0 Number of Tx sequences per TXOP
November 2003 STA0 Number of Tx sequences per TXOP Adrian Stephens, Intel
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STA0 Number of retransmission attempts
November 2003 STA0 Number of retransmission attempts Adrian Stephens, Intel
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November 2003 STA1 Rx Rate Adrian Stephens, Intel
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November 2003 STA1 Tx Burst Size Adrian Stephens, Intel
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STA1 Medium Access Delay
November 2003 STA1 Medium Access Delay Adrian Stephens, Intel
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STA1 Number of retransmission attempts
November 2003 STA1 Number of retransmission attempts Adrian Stephens, Intel
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November 2003 STA10 Rx Rate Adrian Stephens, Intel
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November 2003 STA10 End to End Delay Adrian Stephens, Intel
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November 2003 STA11 Tx Burst Size Adrian Stephens, Intel
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STA11 Tx Media Access Delay
November 2003 STA11 Tx Media Access Delay Adrian Stephens, Intel
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STA11 Tx Undelivered MPDUs per Burst
November 2003 STA11 Tx Undelivered MPDUs per Burst Adrian Stephens, Intel
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STA11 Tx sequences per TXOP
November 2003 STA11 Tx sequences per TXOP Adrian Stephens, Intel
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STA11 Tx Retransmission Attempts
November 2003 STA11 Tx Retransmission Attempts Adrian Stephens, Intel
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November 2003 STA3 Rx Rate Adrian Stephens, Intel
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November 2003 STA3 Tx Burst Size Adrian Stephens, Intel
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November 2003 STA3 Media Access Delay Adrian Stephens, Intel
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STA3 Retransmission Attempts
November 2003 STA3 Retransmission Attempts Adrian Stephens, Intel
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November 2003 STA4 Rx Rate Adrian Stephens, Intel
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November 2003 STA5 Rx rate Adrian Stephens, Intel
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STA5 Medium Access Delay
November 2003 STA5 Medium Access Delay Adrian Stephens, Intel
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STA5 Retransmission Attempts
November 2003 STA5 Retransmission Attempts Adrian Stephens, Intel
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November 2003 STA6 Rx Rate Adrian Stephens, Intel
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November 2003 STA6 Media Access Delay Adrian Stephens, Intel
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STA6 Retransmission Attempts
November 2003 STA6 Retransmission Attempts Adrian Stephens, Intel
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November 2003 STA7 Rx Rate Adrian Stephens, Intel
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November 2003 STA7 Burst Size Adrian Stephens, Intel
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November 2003 STA7 Media Access Delay Adrian Stephens, Intel
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STA7 Retransmission Attempts
November 2003 STA7 Retransmission Attempts Adrian Stephens, Intel
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November 2003 STA8 Rx Rate Adrian Stephens, Intel
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November 2003 STA8 Burst Size Adrian Stephens, Intel
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STA8 Medium Access Delay
November 2003 STA8 Medium Access Delay Adrian Stephens, Intel
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STA8 Retransmission Attempts
November 2003 STA8 Retransmission Attempts Adrian Stephens, Intel
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November 2003 STA9 Rx Rate Adrian Stephens, Intel
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November 2003 STA9 Burst Size Adrian Stephens, Intel
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STA9 Medium Access Delay
November 2003 STA9 Medium Access Delay Adrian Stephens, Intel
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STA9 Retransmission Attempts
November 2003 STA9 Retransmission Attempts Adrian Stephens, Intel
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Detailed results for SS # 4
November 2003 Detailed results for SS # 4 Adrian Stephens, Intel
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November 2003 Aggregate throughput Adrian Stephens, Intel
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November 2003 STA0 Adrian Stephens, Intel
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November 2003 STA0 Adrian Stephens, Intel
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November 2003 STA0 Adrian Stephens, Intel
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November 2003 STA0 Adrian Stephens, Intel
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November 2003 STA0 Adrian Stephens, Intel
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November 2003 STA1 Adrian Stephens, Intel
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November 2003 STA1 Adrian Stephens, Intel
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November 2003 STA1 Adrian Stephens, Intel
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November 2003 STA1 Adrian Stephens, Intel
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November 2003 STA10 Adrian Stephens, Intel
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November 2003 STA2 Adrian Stephens, Intel
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November 2003 STA2 Adrian Stephens, Intel
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November 2003 STA2 Adrian Stephens, Intel
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November 2003 STA2 Adrian Stephens, Intel
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November 2003 STA25 Adrian Stephens, Intel
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November 2003 STA25 Adrian Stephens, Intel
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November 2003 STA25 Adrian Stephens, Intel
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November 2003 STA25 Adrian Stephens, Intel
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November 2003 STA26 Adrian Stephens, Intel
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November 2003 STA26 Adrian Stephens, Intel
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November 2003 STA26 Adrian Stephens, Intel
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November 2003 STA27 Adrian Stephens, Intel
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November 2003 STA27 Adrian Stephens, Intel
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November 2003 STA28 Adrian Stephens, Intel
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November 2003 STA28 Adrian Stephens, Intel
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November 2003 STA28 Adrian Stephens, Intel
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November 2003 STA28 Adrian Stephens, Intel
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November 2003 STA29 Adrian Stephens, Intel
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November 2003 STA3 Adrian Stephens, Intel
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November 2003 STA30 Adrian Stephens, Intel
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November 2003 STA4 Adrian Stephens, Intel
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November 2003 STA6 Adrian Stephens, Intel
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November 2003 STA7 Adrian Stephens, Intel
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November 2003 STA8 Adrian Stephens, Intel
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November 2003 STA9 Adrian Stephens, Intel
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