1. Alpha Blending and Smoothing
Team M3:
Richard Bohn (M31)
Diana Henderson (M32)
Andi Hermawan (M33)
Jenneca Ward (M34)
Overall Project Objective:
Design a portion of a mobile graphics card, performing alpha blending and smoothing operations using minimal area and power.
Stage:
Short Final
Presentation,
4/14/03
Design Manager:
David Jou

2. What is Alpha Blending?
Merging two images together, giving images a degree of transparency
Combines semi-transparent foreground with background color to create an in-between blend
Useful to gradually fade images together

3. What about Smoothing?
Removes the sharp edges in an image, making it more appealing to the eye
Often used for fonts

4. Applications
World of mobile gaming rapidly expanding on both PDA and cell phone platforms.

5. Alpha Blending α
1-α * * +
Alpha-Blended Pixel

6. Hardware: Block Diagram for One Colorα B
RegFile 2 R 1 R 2 1 3 2 1 R 3 2 1 R 3 2 1 R 3 2 1 R R 3 2 3 2 R 4 3 2 R 4 3 R R 5 4 3 5 4 3 R 5 4 3 R 5 4 3 R
RegFile 1 R R R R R R 5 4 R
The RegFiles help in the smoothing process 5 R R R 6 R R 7 6 R 8 7 R R A R 8 R
2:1 MUX
2:1 MUX α
Instr P1
A*B P2 α
OUT

7. Smoothing Algorithm RegFile 1 RegFile 2 Stream in User’s Pixel
Store average of surrounding pixels
Pixel X puts 1/8 of its value in all surrounding pixels X
RegFile 2
X/8
X/8
X/8
X/8
X/8
X/8
X/8
X/8

8. Hardware: The Big Picture
Reset
Clock
6 - Bit Alpha
1-Bit Out Valid
Our Chip(s)
1-Bit Instruction
1-Bit In Ready
16 Bit Pixel A
16-Bit Output
16 Bit Pixel B

9. How Do We Get This to Work?

10. Portion of C Model

11. Portion of C-Model Output

12. Portion of Behavioral Verilog code

13. Behavioral Verilog Simulation Results

14. Structural Verilog Code

15. Verilog Simulation Results

16. Transistor Count Evolution
SRAM (64x16 bits)
7,000 Transistors
ROM
100 Transistors
30 6-bit Fractional Multipliers
10,000 Transistors
27 6-bit Adders
3500 Transistors
Control
2000 Transistors
Registers
3000 Transistors
Total
25600 Transistors

17. Transistor Count Evolution
CHANGE: 6-bit Fractional Multipliers
2000 Transistors
SIGNIFICANT DECREASE!!
27 6-bit Adders
3500 Transistors
Control
Registers:
32 16-bit registers replaced SRAM
10000 Transistors
Total
17500 Transistors

18. Transistor Count Evolution
Part
Transistors
Quantity
Total
2:1 Mux 60 6
360
4:1 Mux
144 3
432
Adder
168 27
4536
Multiplier
940
5640
Register 90 93
8370
Counter
210 2
420
Control
2000 1
TOTAL
21758

19. Transistor Count Evolution
Part
Transistors
Quantity
Total
2:1 Mux 36 6
108
4:1 Mux
132 3
396
Adder
168 27
4536
Multiplier
940
5640
Register 90 93
8370
Counter
210 2
420
Control
178 1
TOTAL
19648

20. Transistor Count Evolution Ends
Part
Transistors
Quantity
Total
2:1 Mux 36 6
108
4:1 Mux
132 3
396
Adder
168 27
4536
Multiplier
940
5640
Register 90 93
8370
Counter
210 2
420
Control
178 1
TOTAL
19648
NEED TO UPDATE!!
w/Final trans. counts

21. Original Floor Plan (Components)
114 15
236 7
2:1 Mux 13
I/O Register 25
118
4:1 Mux 15
Reg File 2
200
106
Reg File 1 21
Adder
157
115
114
180
Multiplier
249 39
Counter
Control Logic
157

22. Original Floor Plan (Module)
370
Register (Pixel 1)
Register (Pixel 2)
Reg File 2
Reg File 1
Register (Alpha)
Routing
Routing
470
2:1 Mux
2:1 Mux
Multiplier
Multiplier
Multiplier
Adder
Register (Output)

23. Original Floor Plan (System)
740
Module 1
(Red)
Module 2
(Blue)
840
Control Logic
Module 3
(Green)
Area:
621,600 µm2
Aspect Ratio:
1.135:1

24. Updated Floor Plan (Module)

25. Register Modified Floor Plan

26. Finalized Floorplan (Module)

27. Updated Floor Plan (System)
Red Module
Area:
353,500 µm2
Aspect Ratio:
1.386:1
Blue Module
505 µm
Green Module
Control Logic/Counter

28. Schematics

29. Half Adder Schematic

30. 2:1 Mux (6-bit)

31. 4:1 Mux (6-bit)

32. Multiplier (6 x 6)

33. Ripple Carry Adder (6-bit)

34. Register (6-bit)

35. RegFile1

36. RegFile2

37. Control Logic

38. Counter

39. Overall Schematic Red Module Input (Pixel A) Input (PixelB) Output
Control Logic
Green Module
Alpha
Blue Module

40. Layouts

41. Half Adder Layout

42. Full Adder
Final Design:

43. 2:1 Mux (6-bit)
Original Design:
Final Design:

44. 4:1 Mux (6-bit)
Original Design:
Final Design:

45. Multiplier (6 x 6)
Final Design:

46. Ripple Carry Adder (6-bit)
Final Design:

47. Register (1-bit)
Final Designs

48. Register (6-bit)
Final Designs:

49. RegFile1
Final Design:

50. RegFile2
Final Design:

51. Control Logic
Original Design
Final Design

52. Counter6
Original Design:
Final Design:

53. Overall Chip Layout
753 um
543 um

54. Component Schematic/Layout Verification

55. 6-bit 2:1 Mux – 1 GHz Schematic Simulation Extracted Simulation
Rise Time: ps
Rise Time: ps

56. 6-bit 2:1 Mux - Outputs

57. 6-bit 4:1 Mux – 500 MHz Schematic Simulation Extracted Simulation
Rise Time: ps
Rise Time: ps

58. 6-bit 4:1 Mux - Outputs

59. Ripple Carry Adder – 350 MHz
Schematic Simulation
Extracted Simulation
Rise Time: ps
Rise Time: ps

60. Ripple Carry Adder - Outputs

61. Register – 833 MHz
Rise Time: ps

62. RegFile1 – 833 MHz
Rise Time: ps

63. RegFile2 – 200 Mhz

64. Control Logic – 500 MHz Schematic Simulation Extracted Simulation
Rise Time: ps
Rise Time: ps

65. Control Logic – Outputs

66. Control Logic – Outputs (cont)

67. Counter – 20 MHz Schematic Simulation Extracted Simulation
Rise Time: ps
Rise Time: ns

68. Counter - Outputs

69. Full Adder – 600 MHz Schematic Simulation Extracted Simulation
Rise Time: ps
Rise Time: ps

70. Full Adder Outputs

71. Full Chip Verification

72. Schematic Simulation Entire Chip - Inputs (50 MHz)

73. Schematic Simulation Entire Chip - Inputs (50 MHz)

74. Schematic Simulation Entire Chip - Outputs (50 MHz)

75. Schematic Simulation Entire Chip - Outputs (50 MHz)

76. Extracted Simulation Entire Chip – Outputs (50 MHz) at 2.4 Volts

77. Extracted Simulation Entire Chip – Outputs (50 MHz) at 2.4 Volts

78. Extracted Simulation Entire Chip – Outputs (50 MHz) at 2.35 Volts

79. Extracted Simulation Entire Chip – Outputs (50 MHz) at 2.35 Volts

80. Extracted Simulation Entire Chip – Outputs (50 MHz) BAD 2.0V

81. Extracted Simulation Entire Chip – Outputs (50 MHz) BAD 2.0V

82. Average Power vs. VDD – Summary
Good
Bad

83. Questions?