1. Modeling and Simulation Issues of Programmable Architectures
Andreas Hoffmann Achim Nohl, Gunnar Braun Oliver Wahlen, Andreas Ropers Prof. Heinrich Meyr
Integrated Signal Processing Systems (ISS) Aachen University of Technology Germany

2. Outline Introduction Model requirements LISA approach
Retargetable development tools
Case studies
Future research

3. Exploration by Iterative Improvement
Complete tool-suite required
HLL-compiler
assembler, linker
simulator
Application
Profiling
Design
criterias met ?
Assembler
regs
data
mem
prog
pipeline control
IF/ID
ID/EX
EX/WB
seq
ASIP Core
Linker
Simulator

4. SW development tools usually written by hand
extremely error-prone
tedious and lengthy process
difficulty of matching the tools to the abstract model of the processor architecture
verification against golden model
generic approach
formalized processor description (LISA)

5. Design Space Exploration with LISA
RESOURCES {
REGISTER
int reg[0..16];
PROGRAM_MEMORY prog_mem;
DATA_MEMORY data_mem; }
OPERATION ALU1
....
LISA
RESOURCES {
REGISTER
int reg[0..32];
PROGRAM_MEMORY prog_mem;
DATA_MEMORY data_mem; }
LISA
OPERATION ALU1
{ .... }
Application
assembler #2
linker #2
simulator #2
assembler #1
linker #1
simulator #1
Profiling
Design
criterias met ?
generic assembler
regs
data
mem
prog
pipeline control
IF/ID
ID/EX
EX/WB
seq
ASIP Core
generic linker
generic simulator

6. Model requirements

7. abstraction of architecture
Abstraction Levels
abstraction of architecture
interrupt
control
I/O
instruction-pipeline
architecture
model
caches
peripherals
instruction
set model
program
sequencer
memory
data
data-paths
data-flow
model

8. high-level language statement
Abstraction Levels (2)
abstraction of time
abstraction
level
high-level language statement
...
instruction
...
cycle
...
phase
...
time

9. Model Components of SW Tools
Memory model
registers, memories
bit widths, ranges
Resource model
hardware resources
resource requirements of operations
Behavioral Model
abstracted hardware activities (various levels)
changing the system state
Instruction-set model
composed of valid HW operations
assembly syntax
instruction word coding
instruction semantics
Timing model
activation sequence of hardware operations
pipeline

10. LISA Approach

11. LISA Approach Joint HW/SW model instruction set processor architecture
LISA description

12. LISA Description Components - HW
Processor Architecture Description
mixed behavioral/structural model
based on C/C++
VLIW support
fixed-point data types
enriched by timing information
allow instruction/cycle/phase-accurate models
predefined pipeline operations
processor
architecture
(HW)

13. LISA Description Components - SW
Instruction Set Description
instruction word coding
variable widths
multiple words
assembly syntax
mnemonic based syntax
algebraic (C-like) syntax
instruction semantics
basic functionality
configurable instruction set information (power, etc.)
instruction
set
(SW)

14. Retargetable development tools

15. Retargetable Environment
LISA
processor
description
Generic
processor
model
LISA compiler lc
Processor model (intermediate representation)
generator generator generator generator
Simulator
debugger
frontend
LISA
description
Debugger
Assembler/
Linker
Disassembler
Co-simulation
interface

16. Target-Independent Debugger

17. Retargetable LISA Assembler & Linker
features
support of 30 common assembler directives
labels and symbols, named user sections
detailed error report/debugging facilities
adapted for embedded systems
driven by the LISA linker command file
linking sections into separate address spaces
paging support
support of user defined memory models
executable generated in COFF

18. LISA model debugger

19. LISA Model Debugging Breakpoint LISA source code
LISA operation execution stack
Control panel
System messages
Instruction registers
Assembly input

20. Design effort - efficiency

21. Case Studies ARM 7 Texas Instruments C6201 instruction-accurate model
4000 lines of LISA and C code (164kB) (incl. comments & empty lines)
design effort: 2 weeks
Texas Instruments C6201
cycle-accurate model
9978 lines of LISA and C code (253kB) (incl. comments & empty lines)
design effort: 6 weeks

22. Model Design Effort: A Comparison
TI C54x: cycle-accurate model Development & verification
handwritten: 20 months (only cycle accurate simulator)
LISA: 2 months
generated tools:
simulator
debugger
co-simulation interface
assembler, linker
model changes take minutes
10x improved designer
efficiency!

23. Case studies: TI C62x DSP (phase), TI C54x DSP (cycle), ARM7 (cycle count)

24. Simulation of TI C6201 model
TI sim62x
LISA simulator
450
400
350
300
Host:
Sun Ultra Sparc 10
300 MHz, 256MB
Solaris 2.7
Speed in KIPS
250
200
150
100 50
FIR
ADPCM
GSM

25. Simulation of TI C54x model
ADPCM codec simulation
4500
4000
3500
Host:
Sun Ultra Sparc 10
300 MHz, 256MB
Solaris 2.7
3000
2500
Speed in KIPS
2000
1500
1000
500
Texas Instr.
sim54x
LISA dynamic
Scheduling
LISA static
Scheduling

26. Simulation of ARM7 model40
Instruction-based
Code Translation 35
Dynamic Scheduling
ARM7 Simulator 30
Hardware at 25 MHz
Host:
AMD Athlon
800 MHz, 256MB
Windows 2000 25
Speed in MIPS 20 15 10
Sehr, sehr schnell !!
ARM7 Microprocessor Hardware läuft mit 17 MIPS bei 25 MHz (siehe ARM7 Datenblatt)
Bei 800 MHz Simulations-Host und vereinfachter Annahme, daß auf Host eine Instruktion pro Zyklus abgearbeitet wird: nur 32 Instruktionen auf Host um 1 Instruktion des ARM7 zu simulieren
Achsen muessen erklärt werden
Welcher Simulations-Host ? 5
FIR
ADPCM
ATM-QFC

27. Summary &
outlook

28. Outlook Summary Future research
software development tools can be generated from LISA
simulator, assembler, linker and debugger
tools proved to be “production quality”
Future research
modeling & simulation of processor architectures
extend pool of processor architectures (DSP & µC)
HW synthesis of pipeline control and instruction decoder
automatic test pattern generation
retargetable compilation