1. Design and Characterisation of the Monolithic Matrices of the H35DEMO Chip
R. Casanova, E. Cavallaro, F. Forster, S. Grinstein, I. Peric,
C. Puigdengoles, S. Terzo, E. Vilella

2. The way to the high luminosity
Motivation
The way to the high luminosity
Replace the whole ATLAS Inner Detector with a new full-silicon Inner Tracker (ITk)
Energy:
8 TeV
13-14 TeV
Luminosity:
LS1
LS2
LS3
1034
> 1034 cm-2s-1
2.5x1034 cm-2s-1
5x1034 cm-2s-1
New layout with 5 pixel barrel layers & large η coverage
Sensor technologies under investigation:
Outer pixel layers (large area to cover)
HR/HV-CMOS pixel detectors
n-in-p planar silicon sensors (150 µm thick)
Inner pixel layers
Thin n-in-p planar silicon sensors (100 µm thick)
3D silicon sensors (baseline for the innermost layer)
From 1e15 neqcm-2…
Radiation fluence
…up to 1.7e16 neqcm-2

3. Monolithic detector (MAPS)
Hybrid vs. monolithic
Readout chip
Bump-bond connection
electronics
Silicon
sensor
Hybrid detector
Sensor + chip
PRO:
Sensor and chip can be optimized separately  radiation hardness  high rate capability (MHz/mm2)
Complex signal processing already in the pixel cell
CON:
Relatively large material budget  multiple scattering
Complex production and assembly  expensive!!
Monolithic detector (MAPS)
All in one piece
PRO:
Commercial technology
No interconnection costs  cost effective!!
Low material budget  low multiple scattering
CON:
Functionalities limited by the size of pixel and dead area at the periphery
Signal obtained by diffusion
 slow!!
 not radiation hard!!

4. Monolithic detector (MAPS)
Hybrid vs. monolithic
Readout chip
Bump-bond connection
electronics
Silicon
sensor
Hybrid detector
Sensor + chip
PRO:
Sensor and chip can be optimized separately  radiation hardness  high rate capability (MHz/mm2)
Complex signal processing already in the pixel cell
CON:
Relatively large material budget  multiple scattering
Complex production and assembly  expensive!!
Monolithic detector (MAPS)
All in one piece
PRO:
Commercial technology
No interconnection costs  cost effective!!
Low material budget  low multiple scattering
CON:
Functionalities limited by the size of pixel and dead area at the periphery
Signal obtained by diffusion
 slow!!
 not radiation hard!!
How to overcome these limitations in the present CMOS technology?
Smaller and more radiation hard electronics
CMOS process can go down to 150 nm and less
Depleted Monolithic Active Pixels Sensors (DMAPS)
High voltage
High resistivity

5. H35DEMO AMS 0.35 µm High Voltage CMOS
Different resistivities: 20–80–200–1000 Ω·cm
Designed by KIT, IFAE and Univ. of Liverpool
Flavour 1
Flavour 2
Monolithic nMOS matrix:
Digital pixels with in-pixel nMOS comparator
Two flavors: with and without Time Walk compensation
Analog matrices (2 arrays):
Different flavors in terms of gain and speed
To be Capacitive Coupled (CC) to FE-I4 readout chips (pitch 50x250 µm2)
Monolithic CMOS matrix:
Analog pixels with off-pixel CMOS comparator
One comparator in the left sub-matrix
Two comparators in the right sub-matrix
Test structures without electronics
Flavour 3
Flavour4
Flavour 5
Flavour 6
Flavour 7
Flavour 8
Left
Right

6. Pixel
*from E. Vilella
Pixel size is the same as the present ATLAS sensor in IBL: 50x250 μm2
Electronics inside a deep n-well which is used as collecting electrode
Substrate of PMOS transistors connected to the collecting electrode (no isolation layer)
p-substrate + 3 separate deep n-wells* to reduce the sensor capacitance
Less noise, better timing - power consumption
Dimensions depend on the in-pixel functionalities
Bias voltage applied from the top (single side processing):  Cheaper  Non-uniform electric field
*all matrices but monolithic nMOS

7. Standalone matrices Analog matrix size: 300 x 16 pixels
BIAS
150x16 pixel matrix
150x16 pixel matrix CU
ROC + EOC
ROC + EOC
Analog matrix size: 300 x 16 pixels
Analog electronics on pixel
Digital electronics on the periphery:
ReadOut Cell (ROC)
End Of Column (EOC)
Control unit (CU)
40 ROC per column
2.5 pixel columns connected to 1 ROC column

8. Analog frontend electronics
nMOS matrix
2 pixel flavours:
nMOS comparator
nMOS comparator with time walk compensation
nMOS comparator output non CMOS  converted to CMOS at the ROC cell
CMOS matrix
No discriminator on pixel placed at ROC
ROC
Analog electronics described in E. Vilella et. al, JINST11, (2016) C01012

9. Readout Cell FEI3 digital readout electronics Asynchronous readout
8-b time stamp
Dynamic RAM memory
Priority NAND-NOR

10. Readout Cell FEI3 digital readout electronics Asynchronous readoutM0 M1
FEI3 digital readout electronics
Asynchronous readout
8-b time stamp
Dynamic RAM memory
Priority NAND-NOR M2
Pull down transistor at EOC

11. End Of Column
EOC stores the Address and Time Stamp (16-bit) of the pixel with the hit flag asserted with the highest priority in the column
Shift register formed by 60 EOC and operated at 40MHz
Address and Time Stamp serialized at 320MHz

12. Readout Control Unit Simple readout: External 320MHz clock (no PLL)
No trigger
No buffering
No zero suppression
External 320MHz clock (no PLL)
4 LVDS serial link at 320Mb/s
Operating frequency: 40MHz (clock divider)
Readout loop:
The address and the time stamp of the pixel with the hit flag asserted with the highest priority in the column are stored in the EOC (1 clock cycle)
Data stored in the EOC is shifted and serialized
When the content of the 60 EOC has been serialized the loop starts again

13. Readout
Example
H11
HN1
H12
H21
H22
HN2

14. Readout
1. The hit with highest priority in the column is stored in the EOC
H12
H22
HN2
H11
H21
HN1

15. End Of Column
2. Data stored in the EOC cells is shifted and serialized
H12
H22
HN2
H21
H31
H11 TS
H11 ADDR

16. End Of Column
2. Data stored in the EOC cells is shifted and serialized
H12
H22
HN2
H31
H41
H21 TS
H21 ADDR

17. End Of Column
3. The content of the last EOC cells is serialized and new hits are stored
HN1 TS
H12
H22
HN2
HN1 ADDR

18. End Of Column
4. The loop starts again
H21 TS
H22
H23
H21 ADDR

19. Experimental results
To evaluate the performance of the H35demo, we proceeded in two ways:
Study charge collection in the bulk: 
Done with the TCT (transient current technique), studying the signal induced by lasers on diode-like structures
Study the overall performance of the devices in beam test:
Develop readout system for the monolithic matrices
Irradiate some devices
Study performance of unirradiated and irradiated devices in beam test
External pixel readout
Central pixel readout

20. H35DEMO (TCT measurements)
Edge-TCT measurements on 200 Ω·cm test structures:
Irradiated with reactor neutron at JSI (Ljubljana) up to 2e15 neqcm2
Increase of the depletion depth with irradiations up to 1e15 neqcm2
initial acceptor removal effect
Effective doping concentration obtained from:
Initial doping
Acceptor removal
Acceptor introduction
Results published in E. Cavallaro et al., JINST12, (2017) no.01, C01074

21. Monolithic matrix readout at IFAE
Trigger board
Trigger in
Busy out
RJ45
FPGA board
Xilinx ZC706
Adapter PCBs
1x H35 PCB
1x test signals
1x trigger board
H35demo chip
Both CMOS and nMOS matrices wire-bonded
External
Pulse generator
Power supplies
H35demo PCB
Voltage regulators
Sensor bias input
Injection pulse input
Analog signal output
PCBs, FPGA firmware and software developed at IFAE

22. Beam test setup Beam test at Fermilab
H35
Beam test at Fermilab
120 GeV protons
In collaboration with UniGe & Argonne
Un-irradiated and very first time irradiated H35DEMO monolithic matrices
IFAE readout system for the H35DEMO monolithic matrices* +
UniGe FE-I4 telescope** for tracking (6 planes)
H35
*S.Terzo et al., JINST 12 (2017) no.6, C06009
**M.Benoit et al., JINST11 (2016) no.7, P07003

23. Hit efficiency results
Monolithic CMOS matrix
Slightly different behavior of left and right part
Sampling clock
Threshold tuning
Observable especially with low signals/high thresholds
Before irradiation
Uniform efficiency
For ρ ≥ 80 Ωcm
Efficiency > 99%
for Vbias ≥ 50 V
For ρ = 20 Ωcm
Efficiency reach 99% at 160 V
Depletion depth too low up to 100 V (Difference between left and right part of the matrix)

24. Irradiated detectors
Chips were irradiated with neutrons in the TRIGA reactor in Ljubljana
After irradiation to 5e14 neqcm-2
For ρ = 200 Ω·cm
Efficiency > 90% for Vbias ≥ 80 V
Noise? Readout architecture limitations? Better parameter calibration after irradiation?
Next beam test at CERN SpS in few weeks
Improved firmware
Higher irradiated modules
1e15, 1.5e15, 2e15 neqcm-2
Also to measure nMOS matrices 20

25. Summary
First large area depleted-CMOS prototype to investigate feasibility of this technology for the ATLAS tracker upgrade has been developed
H35DEMO standalone matrices have been described
Readout system developed, verified H35demo functionality
Charge collection before and after irradiation studied
First test beam measurements of a monolithic device presented
Excellent performance before irradiation
Very good results after irradiation for this prototype! Eff > 90% after 5e14neqcm-2 and 200Ω·cm
Further tests at CERN during the coming weeks
New radiation hard prototypes being developed in AMS 0.18µm HVCMOS technology: ATLASPix family

26. Backup slides

27. Mesured chips Name Resistivity Irradiation PCB Comments UniGe-80-2
80 Ωcm
n/a
Old (v1)
measured D5
200 Ωcm
New (v2)
UniGe-20-1
20 Ωcm
UniGe-1k-2
1 kΩcm
Early breakdown E2
2e14
Mishandling E3
5e14 E5 E7
1e15 E8
Measured but left matrix very noisy (fixed with new firmware) E9
2e15
Stopped working after shipping to Fermilab
Not irradiated modules: CMOS left + right
Irradiated module: only CMOS right

28. H35DEMO (TCT measurements)
Characterization of H35 test structures:
3x3 pixel structures w/o electronics
External pixels shorted together
Separate readout of the central pixel
The Edge-TCT setup:
Infra-red laser (1064 nm)
Beam spot about 10 µm FWHM
Pulses of about 500 ps
Readout: DRS4 evaluation board
700 MHz bandwidth, 5 GSPS, 200 ns sampling depth
Illumination from the edge to study the depletion depth
FWHM of the charge collection profile of the central pixel is taken as measure of the depletion depth
Central pixel readout
External pixel readout
TCT measurements and irradiations in collaboration with G. Kramberger and I. Mandic (JSI, Ljubljana)

29. Depletion: after irradiation
Irradiation at the TRIGA neutron reactor at JSI, Ljubljana:
Now: 2e14, 5e14, 10e14, 20e14 neqcm-2
Next steps: 5e15 and 1e16 neqcm-2
80 Ωcm
Acceptor removal effect visible for lower substrate resistivities which leads to an increase of the depletion depth after irradiation up to 2e15 neqcm-2
200 Ωcm
Due to the low initial acceptor concentration in the 1000 Ωcm sample the creation of stable acceptors dominates and the depletion depth decreases after irradiation
1000 Ωcm 29