1. TAO1221 COMPUTER ARCHITECTURE AND ORGANIZATION LAB 3 & 4 Part 1
Prisha Palpunavam
Postgraduate Lab 2 FIST (PG LAB 2)

2. INSTRUCTION SET OF 8085
8085 instructions can be classified into several groups: 1. Data Transfer (Copy Operation) 2. Arithmetic 3. Logical and Bit manipulation 4. Branch 5. Machine Control (Input/Output)

3. 1. Data Transfer (Copy Operation) Instruction Set

4. 1. Data Transfer (Copy Operation) Instruction Set
LXI H, 9010H Load immediate 16 bit data into register pair.
STA 4888H Store data from accumulator into memory address, 4888H
LDA 4888H Load data into accumulator using memory location address, 4888H
SHLD 9800H Store H and L direct, assume register H contains 45H and register L contains 98H. Upon executing SHLD 9800H, memory location address 9800H will store 98H and memory location address 9801H will store 45H.

5. 1. Data Transfer (Copy Operation) Instruction Set
LHLD 9800H Load H and L direct. Memory location address 9800H contains 98H and memory location address 9801H contains 45H. Upon executing LHLD 9800H, L register will contain 98H and H register will contain 45H.
LDAX D Load A with contents of the memory location whose address is specified in D. Assume register pair DE contains 8900H (memory location address), this address contains data 38H. After executing LDAX D, accumulator will hold 38H.

6. 1. Data Transfer (Copy Operation) Instruction Set
STAX B Store the contents of the accumulator at memory location address given by register pair (BC or DE only). Assume BC register pair contains 3200H and accumulator holds data of 99H. After executing STAX B, memory location address 3200H will contain 99H.
XCHG Exchanges the contents of register H with register D and exchanges the contents of register L with register E. Assume register pair HL contains 4500H (memory location address) and DE contains 4531H. After executing XCHG, HL register will contain 4531H and DE will contain 4500H.

7. 1.1 PROGRAMMING EXERCISE Question 1 – Exchange the contents/data of memory locations 0001H and 0002H based on direct addressing

9. 1.1 PROGRAMMING EXERCISE Question 2 – Exchange the contents/data of memory locations 0003H and 0004H based on register indirect addressing

11. 2. Arithmetic Operations Instruction Set

12. 2. Arithmetic Operations Instruction Set (Addition)
ADD B Move contents in register B to accumulator then add.
ADD M M is (HL). Contents of memory location address HL is added to accumulator. Then, add contents.
ADI 44H Add immediate, assuming that
accumulator contains 29H, upon executing ADI 44H, accumulator will hold 73H.
ADC B Add register B with carry to accumulator, assuming that A contains 98H and B contains 78H, carry flag is set in previous execution of the instruction. Upon executing the same instruction, A will hold 11H

13. 2. Arithmetic Operations Instruction Set (Addition)
ADC M Add data in memory to A with carry, assuming accumulator holds 88H and memory location 2000H contains 98H, after execution accumulator will contain 00H.
ACI 96H Add immediate data to A with carry, assuming accumulator contains FFH, after execution accumulator holds 95H with active sign, auxiliary carry, parity and carry flags.
DAD B Add register pair to HL, assuming BC contains 2000H and HL contains 2001H. After execution, HL will contain 0000H and carry flag will be set.
DAA Decimal adjust accumulator, adjusts A to packed BCD after addition. Does not convert a binary number into BCD. Works only if BCD numbers are used.

14. 2. 1 PROGRAMMING EXERCISE Question 3 – Add two 8 bit numbers
2.1 PROGRAMMING EXERCISE Question 3 – Add two 8 bit numbers. Assuming the memory location 2000H is loaded with 14H and memory location 2001H is loaded with 89H. Add the contents of memory locations 2000H and 2001H and place the result in memory location 2002H.

16. 2. 2 PROGRAMMING EXERCISE Question 4 – Add two 16 bit numbers
2.2 PROGRAMMING EXERCISE Question 4 – Add two 16 bit numbers. Add the 16-bit number in memory locations 2000H and 2001H to the 16-bit number in memory locations 2002H and 2003H. The most significant eight bits of the two numbers to be added are in memory locations 2001H and 2003H. Store the result in memory locations 2004H and 2005H with the most significant byte in memory location 2005H. [Use DAD instruction set] Sample problem: (4000H) = 15H (4001H) = 1CH (4002H) = B7H (4003H) = 5AH Result = 1C15 + 5AB7H = 76CCH (4004H) = CCH (4005H) = 76H

18. 2. 3 PROGRAMMING EXERCISE Question 5 – Add two 16 bit numbers
2.3 PROGRAMMING EXERCISE Question 5 – Add two 16 bit numbers. Add the 16-bit number in memory locations 2000H and 2001H to the 16-bit number in memory locations 2002H and 2003H. The most significant eight bits of the two numbers to be added are in memory locations 2001H and 2003H. Store the result in memory locations 2004H and 2005H with the most significant byte in memory location 2005H. [Use ADC instruction set] Sample problem: (4000H) = 15H (4001H) = 1CH (4002H) = B7H (4003H) = 5AH Result = 1C15 + 5AB7H = 76CCH (4004H) = CCH (4005H) = 76H

20. 2. Arithmetic Operations Instruction Set (Subtraction)
SUB B Move contents in register B to accumulator then subtract.
SUB M M is (HL). Contents of memory location address HL is subtracted from accumulator. Assume accumulator contains 88H, HL register pair contains F000H and that location contains A0H. Upon execution, accumulator will contain E8H. Carry, Sign and Parity flags are set.
SUI 89H Subtract immediate from accumulator, assuming that accumulator contains 30H, upon executing SUI 60H, accumulator will hold D0H with active Sign flag and Carry flag.

21. 2. Arithmetic Operations Instruction Set (Subtraction)
SBB B Subtract register B from accumulator with borrow. Assuming accumulator contains 08H, C register contains 05H and carry flag is set. Upon execution, accumulator will hold 02H.
SBB M Subtract memory data from accumulator with borrow. Assuming accumulator contains FFH, HL register contains 2000H and memory location contains 00H and carry flag is active. Upon execution, accumulator will hold FEH. Thus, Sign and Auxiliary Carry flags are active
SBI 89H Subtract immediate from accumulator with borrow, assuming that accumulator contains FFH, upon executing SBI 89H, accumulator will hold H with active Parity flag and Auxiliary Carry flag.

22. 2. 3 PROGRAMMING EXERCISE Question 6 – Subtract two 8 bit numbers
2.3 PROGRAMMING EXERCISE Question 6 – Subtract two 8 bit numbers. Subtract the contents of memory location 2001H from the memory location 2000H and place the result in memory location 2002H. Sample problem: (4000H) = 51H (4001H) = 19H Result = 51H – 19H = 38H

24. 2. Arithmetic Operations Instruction Set (Increment/Decrement)
INR B Data stored in register B is incremented by 1.
INR M Contents in HL are incremented by 1.
INX H Increment register pair HL.
DCR A Decrement data in register A by one.
DCR M Decrement data in register A by one.
DCX SP Register pairs are decremented by one.

25. LAB 3- DISCUSSION

26. 2. Differentiate between programming in hardware and programming in software?
Programming in hardware means configuring a small set of basic logic components specifically for a particular computation.
Programming in software means supplying a specific set of control signals to a general-purpose hardware.
Operand – data to be operated on

27. 4. Briefly explain the transfers that must be supported by interconnection structure (e.g. bus)
Memory to processor: The processor reads an instruction or a unit of data from memory. Processor to memory: The processor writes a unit of data to memory. I/O to processor: The processor reads data from an I/O device via an I/O module. Processor to I/O: The processor sends data to the I/O device. I/O to or from memory: For these two cases, an I/O module is allowed to exchange data directly with memory, without going through the processor, using direct memory access (DMA).
Operand – data to be operated on

28. 5. What is the benefit of using multiple-bus architecture compared to single-bus architecture?
With multiple buses, there are fewer devices per bus. This:
reduces propagation delay, because each bus can be shorter
(2) reduces bottleneck effects.
Operand – data to be operated on

29. 6. Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two fields: the first byte contains the opcode and the remainder the immediate operand or an operand address. a) What is the maximum directly addressable memory capacity (in bytes)? b) Discuss the impact on the system speed if the microprocessor bus has: i. a 32-bit local address bus and a 16-bit local data bus, or ii. a 16-bit local address bus and a 16-bit local data bus. c) How many bits are needed for the program counter and the instruction register?
Operand – data to be operated on

30. 6. a) Considering 32-bit system, 2^(32-8), (8 bit = 1 byte for the opcode) 2 ^24 = 16,777,216 bytes = 16MB b) i. If the local address bus is 32 bits, the whole address can be transferred at once and decoded in memory. However, because the data bus is only 16 bits, it will require 2 cycles to fetch a 32-bit instruction or operand. ii. The 16 bits of the address placed on the address bus can't access the whole memory. Thus a more complex memory interface control is needed to latch the first part of the address and then the second part (because the microprocessor will end in two steps). For a 32-bit address, one may assume the first half will decode to access a "row" in memory, while the second half is sent later to access a "column" in memory. In addition to the two-step address operation, the microprocessor will need 2 cycles to fetch the 32-bit instruction/operand. c) The program counter must be at least 24 bits. Typically, a 32-bit microprocessor will have a 32-bit external address bus and a 32-bit program counter, unless on-chip segment registers are used that may work with a smaller program counter. If the instruction register is to contain the whole instruction, it will have to be 32-bits long; if it will contain only the op code (called the op code register) then it will have to be 8 bits long.
Operand – data to be operated on

31. END OF LAB 3 & LAB 4 (Part 1)