1. Typical Timing Specifications
Positive edge-triggered D flip-flop
Setup and hold times
Minimum clock width
Propagation delays (low to high, high to low, max and typical)
Th 5ns
Tw 25ns
Tplh 25ns 13ns
Tphl 40ns 25ns
Tsu 20ns D
CLK Q
all measurements are made from the clocking event that is, the rising edge of the clock
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 2

2. Cascading Edge-triggered Flip-Flops
Shift register
New value goes into first stage
While previous value of first stage goes into second stage
Consider setup/hold/propagation delays (prop must be > hold)
CLK IN Q0 Q1 D Q
OUT
100 IN Q0 Q1
CLK
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 3

3. Cascading Edge-triggered Flip-Flops
Shift register
New value goes into first stage
While previous value of first stage goes into second stage
Consider setup/hold/propagation delays (prop must be > hold)
CLK IN Q0 Q1 D Q
OUT
Clk1
Delay
100 IN Q0 Q1
CLK
Clk1
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 4

4. Cascading Edge-triggered Flip-Flops (cont’d)
Why this works
Propagation delays exceed hold times
Clock width constraint exceeds setup time
This guarantees following stage will latch current value before it changes to new value In Q0 Q1
CLK
Tsu
4ns
Tsu
4ns
timing constraints
guarantee proper
operation of
cascaded components Tp
3ns Tp
3ns
assumes infinitely fast distribution of the clock Th
2ns Th
2ns
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 5

5. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 6
Clock Skew
The problem
Correct behavior assumes next state of all storage elements determined by all storage elements at the same time
Difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic (and will soon become greater than logic delay)
Effect of skew on cascaded flip-flops:
100 In Q0 Q1
CLK0
CLK1
CLK1 is a delayed
version of CLK0
original state: IN = 0, Q0 = 1, Q1 = 1
due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 6

6. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 9
Registers
Collections of flip-flops with similar controls and logic
Stored values somehow related (e.g., form binary value)
Share clock, reset, and set lines
Similar logic at each stage
Examples
Shift registers
Counters R S D Q
OUT1
OUT2
OUT3
OUT4
CLK
IN1
IN2
IN3
IN4
"0"
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 9

7. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 10
Shift Register
Holds samples of input
Store last 4 input values in sequence
4-bit shift register: D Q IN
OUT1
OUT2
OUT3
OUT4
CLK
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 10

8. Shift Register Verilog
module shift_reg (out4, out3, out2, out1, in, clk);
output out4, out3, out2, out1;
input in, clk;
reg out4, out3, out2, out1;
clk)
begin
out4 <= out3;
out3 <= out2;
out2 <= out1;
out1 <= in;
end
endmodule
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 11

9. Shift Register Verilog
module shift_reg (out, in, clk);
output [4:1] out;
input in, clk;
reg [4:1] out;
clk)
begin
out <= {out[3:1], in};
end
endmodule
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 12

10. Universal Shift Register
Holds 4 values
Serial or parallel inputs
Serial or parallel outputs
Permits shift left or right
Shift in new values from left or right
left_in
left_out
right_out
clear
right_in
output
input s0 s1
clock
clear sets the register contents and output to 0 s1 and s0 determine the shift function s0 s1 function hold state shift right shift left load new input
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 13

11. Design of Universal Shift Register
Consider one of the four flip-flops
New value at next clock cycle:
Nth cell
to N-1th cell
to N+1th cell Q D
CLK
clear s0 s1 new value 1 – – output output value of FF to left (shift right) output value of FF to right (shift left) input
CLEAR
s0 and s1 control mux 1 2 3
Q[N-1] (left)
Q[N+1] (right)
Input[N]
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 14

12. Universal Shift Register Verilog
module univ_shift (out, lo, ro, in, li, ri, s, clr, clk);
output [3:0] out;
output lo, ro;
input [3:0] in;
input [1:0] s;
input li, ri, clr, clk;
reg [3:0] out;
assign lo = out[3];
assign ro = out[0];
clk or clr)
begin
if (clr) out <= 0;
else
case (s)
3: out <= in;
2: out <= {out[2:0], ri};
1: out <= {li, out[3:1]};
0: out <= out;
endcase
end
endmodule
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 15

13. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 18
Counters
Sequences through a fixed set of patterns
In this case, 1000, 0100, 0010, 0001
If one of the patterns is its initial state (by loading or set/reset)
Mobius (or Johnson) counter
In this case, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 D Q IN
OUT1
OUT2
OUT3
OUT4
CLK D Q IN
OUT1
OUT2
OUT3
OUT4
CLK
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 18

14. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 19
Binary Counter
Logic between registers (not just multiplexer)
XOR decides when bit should be toggled
Always for low-order bit, only when first bit is true for second bit, and so on D Q
OUT1
OUT2
OUT3
OUT4
CLK
"1" =
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 19

15. Binary Counter Verilog
module shift_reg (out4, out3, out2, out1, clk);
output out4, out3, out2, out1;
input in, clk;
reg out4, out3, out2, out1;
clk)
begin
out4 <= (out1 & out2 & out3) ^ out4;
out3 <= (out1 & out2) ^ out3;
out2 <= out1 ^ out2;
out1 <= out1 ^ 1b’1;
end
endmodule
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 20

16. Binary Counter Verilog
module shift_reg (out4, out3, out2, out1, clk);
output [4:1] out;
input in, clk;
reg [4:1] out;
clk)
out <= out + 1;
endmodule
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 21

17. Sequential Logic Summary
Fundamental building block of circuits with state
Latch and flip-flop
R-S latch, R-S master/slave, D master/slave, edge-triggered D FF
Timing methodologies
Use of clocks
Cascaded FFs work because prop delays exceed hold times
Beware of clock skew
Basic registers
Shift registers
Pattern detectors
Counters
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 24

18. Sequential Logic Implementation
Models for representing sequential circuits
Finite-state machines (Moore and Mealy)
Representation of memory (states)
Changes in state (transitions)
Design procedure
State diagrams
State transition table
Next state functions
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 25

19. Abstraction of State Elements
Divide circuit into combinational logic and state
Localize feedback loops and make it easy to break cycles
Implementation of storage elements leads to various forms of sequential logic
Combinational Logic
Storage Elements
Outputs
State Outputs
State Inputs
Inputs
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 26

20. Forms of Sequential Logic
Asynchronous sequential logic – state changes occur whenever state inputs change (elements may be simple wires or delay elements)
Synchronous sequential logic – state changes occur in lock step across all storage elements (using a periodic waveform - the clock)
Clock
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 27

21. Finite State Machine Representations
States: determined by possible values in sequential storage elements
Transitions: change of state
Clock: controls when state can change by controlling storage elements
Sequential Logic
Sequences through a series of states
Based on sequence of values on input signals
Clock period defines elements of sequence
In = 0
In = 1
100
010
110
111
001
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 28

22. Example Finite State Machine Diagram
Combination lock
reset S3
closed
mux=C1
equal & new
not equal & new
not new S1 S2
OPEN
ERR
mux=C2
mux=C3
open
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 29

23. Can Any Sequential System be Represented with a State Diagram?
Shift Register
Input value shown on transition arcs
Output values shown within state node D Q IN
OUT1
OUT2
OUT3
CLK 1
100
110
111
011
101
010
000
001
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 30

24. Counters are Simple Finite State Machines
Proceed thru well-defined state sequence in response to enable
Many types of counters: binary, BCD, Gray-code
3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...
3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...
010
100
110
011
001
000
101
111
3-bit up-counter
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 31

25. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 32
Verilog Upcounter
module binary_cntr (q, clk)
inputs clk;
outputs [2:0] q;
reg [2:0] q;
reg [2:0] p;
//Calculate next state
case (q)
3’b000: p = 3’b001;
3’b001: p = 3’b010; …
3’b111: p = 3’b000;
endcase
clk) //next becomes current state
q <= p;
endmodule
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 32

26. How Do We Turn a State Diagram into Logic?
Counter
Three flip-flops to hold state
Logic to compute next state
Clock signal controls when flip-flop memory can change
Wait long enough for combinational logic to compute new value
Don't wait too long as that is low performance D Q
OUT1
OUT2
OUT3
CLK
"1"
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 33

27. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 34
FSM Design Procedure
Start with counters
Simple because output is just state
Simple because no choice of next state based on input
State diagram to state transition table
Tabular form of state diagram
Like a truth-table
State encoding
Decide on representation of states
For counters it is simple: just its value
Implementation
Flip-flop for each state bit
Combinational logic based on encoding
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 34

28. FSM Design Procedure: State Diagram to Encoded State Transition Table
Tabular form of state diagram
Like a truth-table (specify output for all input combinations)
Encoding of states: easy for counters – just use value
current state next state
010
100
110
011
001
000
101
111
3-bit up-counter
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 35

29. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 36
Implementation
D flip-flop for each state bit
Combinational logic based on encoding
notation to show
function represent input to D-FF
C3 C2 C1 N3 N2 N
N1 := C1'
N2 := C1C2' + C1'C2
:= C1 xor C2
N3 := C1C2C3' + C1'C3 + C2'C3
:= C1C2C3' + (C1' + C2')C3
:= (C1C2) xor C3
0 0
0 1
1 1 C1 C2 C3 N3
0 1
1 0 C1 C2 C3 N2
1 1
0 0 C1 C2 C3 N1
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 36

30. Implementation (cont'd)
Programmable Logic Building Block for Sequential Logic
Macro-cell: FF + logic
D-FF
Two-level logic capability like PAL (e.g., 8 product terms)
D Q Q
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 37

31. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 43
State Machine Model
Values stored in registers represent the state of the circuit
Combinational logic computes:
Next state
Function of current state and inputs
Outputs
Function of current state and inputs (Mealy machine)
Function of current state only (Moore machine)
Inputs
Outputs
Next State
Current State
output logic
next state logic
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 43

32. State Machine Model (cont’d)
Inputs
Outputs
Next State
Current State
output logic
next state logic
States: S1, S2, ..., Sk
Inputs: I1, I2, ..., Im
Outputs: O1, O2, ..., On
Transition function: Fs(Si, Ij)
Output function: Fo(Si) or Fo(Si, Ij)
Clock
Next State
State 1 2 3 4 5
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 44

33. Example: Ant Brain (Ward, MIT)
Sensors: L and R antennae, 1 if in touching wall
Actuators: F - forward step, TL/TR - turn left/right slightly
Goal: find way out of maze
Strategy: keep the wall on the right
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 45

34. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 46
Ant Brain
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 46

35. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 47
Ant Behavior
A: Following wall, touching Go forward, turning left slightly.
If R and not L, go to A
If R and L , go to E
else go to B
B: Following wall, not touching Go forward, turning right slightly
if R, go to A
if not R, go to C
C: Break in wall Go forward, turning right slightly
if R, go to A
if not R, stay in C
E: Wall in front or on left Turn left
If L or R, stay in E
Otherwise, go to B
LOST: Forward until we touch something
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 47

36. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 48
Designing an Ant Brain
State Diagram
L + R
L’ R
LOST
(F)
L’ R’
E (TL)
L + R R A
(TL, F) L
L’ R’ B
(TR, F)
L’ R’ R
C (TR, F) R’ R’
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 48

37. Synthesizing the Ant Brain Circuit
Encode States Using a Set of State Variables
Arbitrary choice - may affect cost, speed
Use Transition Truth Table
Define next state function for each state variable
Define output function for each output
Implement next state and output functions using combinational logic
2-level logic (ROM/PLA/PAL)
Multi-level logic
Next state and output functions can be optimized together
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 49

38. Transition Truth Table
Using symbolic states and outputs
LOST
(F)
E (TL) A
(TL, F) B
(TR, F)
C (TR, F) R’
L’ R’ R L
L’ R
L + R
state L R next state outputs
LOST 0 0 LOST F
LOST – 1 E/G F
LOST 1 – E/G F
A 0 0 B TL, F
A 0 1 A TL, F
A 1 – E/G TL, F
B – 0 C TR, F
B – 1 A TR, F
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 50

39. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 51
Synthesis
5 states : at least 3 state variables required (X, Y, Z)
State assignment (in this case, arbitrarily chosen)
LOST - 000
E - 001
A - 010
B - 011
C - 100
state L R next state outputs
X,Y,Z X', Y', Z' F TR TL
it now remains to synthesize these 6 functions
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 51

40. Synthesis of Next State and Output Functions
state inputs next state outputs
X,Y,Z L R X+,Y+,Z+ F TR TL
e.g.
TR = X + Y Z
X+ = X R’ + Y Z R’ = R’ TR
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 52

41. Circuit Implementation
Outputs are a function of the current state only - Moore machine L R F TR TL
Next State
Current State
output logic
next state logic X+ Y+ Z+ X Y Z
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 53

42. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 54
Verilog Sketch
module ant_brain (F, TR, TL, L, R)
inputs L, R;
outputs F, TR, TL;
reg X, Y, Z;
assign F = function(X, Y, Z, L, R);
assign TR = function(X, Y, Z, L, R);
assign TL = function(X, Y, Z, L, R);
clk)
begin
X <= function (X, Y, Z, L, R);
Y <= function (X, Y, Z, L, R);
Z <= function (X, Y, Z, L, R);
end
endmodule
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 54

43. Don’t Cares in FSM Synthesis
What happens to the "unused" states (101, 110, 111)?
Exploited as don't cares to minimize the logic
If states can't happen, then don't care what the functions do
if states do happen, we may be in trouble
000
(F)
001 (TL)
010
(TL, F)
011
(TR, F)
100 (TR, F) R’
L’ R’ R L
L’ R
L + R
111
101
110
Ant is in deep trouble
if it gets in this state
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 55

44. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 56
State Minimization
Fewer states may mean fewer state variables
High-level synthesis may generate many redundant states
Two state are equivalent if they are impossible to distinguish from the outputs of the FSM, i. e., for any input sequence the outputs are the same
Two conditions for two states to be equivalent:
1) Output must be the same in both states
2) Must transition to equivalent states for all input combinations
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 56

45. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 57
Ant Brain Revisited
Any equivalent states?
LOST
(F)
E (TL) A
(TL, F) B
(TR, F)
C (TR, F) R’
L’ R’ R L
L’ R
L + R
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 57

46. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 58
Ant Brain Revisited
Inequivalent since actions differ
LOST
(F)
E (TL) A
(TL, F) B
(TR, F)
C (TR, F) R’
L’ R’ R L
L’ R
L + R
Potentially Equivalent (actions equivalent)
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 58

47. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 59
Equivalence Proof
Equivalent Behavior under R
L + R
L’ R
LOST
(F)
E (TL) A
(TL, F)
L + R L R
L’ R’
L’ R’ R
L’ R’ B
(TR, F)
C (TR, F) R’ R’
Equivalent Behavior under R’
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 59

48. CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 60
New Improved Brain
Merge equivalent B and C states
Behavior is exactly the same as the 5-state brain
We now need only 2 state variables rather than 3
LOST
(F)
E (TL) A
(TL, F)
B/C
(TR, F) R’
L’ R’ R L
L’ R
L + R
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 60

49. New Brain Implementation
state inputs next state outputs
X,Y L R X',Y' F TR TL X X+ Y R L X Y+ Y R L X F Y R L X TR Y R L X TL Y R L
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 61

50. Sequential Logic Implementation Summary
Models for representing sequential circuits
Abstraction of sequential elements
Finite state machines and their state diagrams
Inputs/outputs
Mealy, Moore, and synchronous Mealy machines
Finite state machine design procedure
Deriving state diagram
Deriving state transition table
Determining next state and output functions
Implementing combinational logic
CS Spring 2008 – Lec #6: Moore and Mealy Machines - 62