1. Flip-Flop

2. Objectives Flip-flops
Upon completion of this chapter, you will be able to :
Construct and analyze the operation of a latch flip-flop made from NAND or NOR gates
Identify and understand the operation of RS, JK, D, T flip- flops
Understand edge-triggered flip-flops
Describe the difference between synchronous and asynchronous systems

3. Introduction
Flip-flop is digital circuit which functions as a memory element used in the digital system.
Flip-Flop is made up of an assembly of logic gates. Even though a logic gate, by itself, has no storage capability.
Flip-Flop is also known as latch and bi-stable multi-vibrator.

4. General Flip-flop Symbol
The symbol shows two outputs, labeled Q and Q, that are the inverse of each other
The FF can has one or more inputs. These inputs are used to cause the FF to switch back and forth between its possible output states Q FF
outputs
inputs

5. General Flip-flop Symbol
Flip-Flop has two allowed output states.
SET state :-
where Q = 1and Q = 0.
RESET state :-
where Q = 0 and Q = 1. Q FF
outputs
inputs
Thus, flip-flop is also known as bi-stable multi-vibrator or latch.

6. Various type of Flip-FlopsJ K R S Q Q D Q Q
>
Clk
> T
R S
J K D T
Tutorial

7. RS Flip-Flops FF The most basic flip-flop is RS flip-flop. S R Q
The inputs are labeled as
SET ( S ) and RESET ( R ).
The RS flip-flop can be constructed from logic gates. S R Q
inputs FF
outputs

8. RS Flip-Flops NAND gate FF
The two NAND gates are cross - coupled so that the output of NAND-1 is connected to one of the inputs of NAND-2, and vice versa. S R Q
NAND-2

9. RS Flip-Flops 0 1 S Q R 0 1 NAND gate FF NAND-1 NAND-2
NAND gate FF is an active low FF. S R Q
A logic 0 activates set S
i.e. S = 0 Q = 1
To reset the FF, apply a logic 0 to R
i.e. R = 0 Q = 1
NAND-2
Click TO Continue

10. RS Flip-Flops 0 1 1 0 0 1 1 0 0 1 1 0 0 1 S R Q NAND gate FF NAND-1
Truth table for NAND gate RS FF S R Q
S R Q Q Remarks
Prohibited state
Set state, Q =1
Reset state, Q =1
Unchange / Hold
NAND-2
Click TO Continue

11. RS Flip-Flops FF FF NAND gate FF S R Q Fig A Q S R Fig B inputs
outputs
Fig A
Block logic symbol for RS FF using NAND gate can be as in Fig A
or Fig B. Q FF
outputs S R
inputs
Fig B
Click TO Continue

12. RS Flip-Flops FF Q S R NAND gate FF S R Q Timing diagrams At time :-
T T1 T T T4
At time :-
T0 :- FF is at reset state; i.e. Q=0.
T1 :- reset signal will reset the FF.
T2 :- set signal will set the FF.
T3 :- set signal will set the FF.
T4 :- reset signal will reset the FF. Q
Click TO Continue

13. RS Flip-Flops NOR gate FF
The two NOR gates are cross - coupled so that the output of NOR-1 is connected to one of the inputs of NOR-2, and vice versa.
NOR -1
NOR -2 S R Q

14. RS Flip-Flops S Q R NOR gate FF NOR -1 NOR -2
NOR gate FF is an active HIGH FF.
A logic 1 activates set S
i.e. S = 1 Q = 1
To reset the FF, apply a logic 1 to R
i.e. R = 1 Q = 1
NOR -2
Click TO Continue

15. RS Flip-Flops 0 0 1 1 0 0 0 1 1 1 0 0 1 1 S R Q NOR gate FF NAND-1
Truth table for NOR gate RS FF . S R Q
S R Q Q Remarks
Prohibited state
Set state, Q =1
Reset state, Q =1
Unchange / Hold
NAND-2
Click TO Continue

16. RS Flip-Flops FF NOR gate FF Q S R outputs inputs
Block logic symbol for RS FF using NOR gate Q FF
outputs S R
inputs

17. RS Flip-Flops FF S R Q NOR gate FF S R Q Timing diagrams At time :-
T0 T1 T T3 T4
At time :-
T0 :- FF is at reset state; i.e. Q=0.
T1 :- set signal will set the FF.
T2 :- reset signal will reset the FF.
T3 :- reset signal will reset the FF.
T4 :- set signal will set the FF. Q
Click TO Continue

18. RS Flip-Flops Triggering of FF Clock pulses signal
Flip-flop operates without clock input is called asynchronously.
But most digital systems operate synchronously, that is operate in step with a clock signal.
Flip-flop are mostly triggered by clock pulses.
Click TO Continue

19. RS Flip-Flops Triggering of FF Clock pulses signal
Flip-flop may be positive edge triggered or negative edge edge triggered.
A positive edge-triggered flip-flop transfer data from the input to the output on the leading edge of the clock pulse.
A negative edge-triggered flip-flop transfer data from the input to the output on the falling edge of the clock pulse.
Click TO Continue

20. RS Flip-Flops Q S R Q S R Symbol of edge triggered flip-flop
Positive edge triggered
Negative edge triggered Q S R
Clk Q S R
Clk

21. Logic circuit of edge triggered FF
RS Flip-Flops
Logic circuit of edge triggered FF
Positive edge triggered S Q S R
Clk Q
Clk R

22. Symbol of positive edge-triggered JK FF
JK Flip-Flops
The J and K inputs are the data inputs, and clock input transfers data from inputs of the flip-flop to the outputs in the same ways as RS flip- flop.
The advantage of JK flip-flop is that it does not have the problem of a prohibited input combinations found in RS flip-flop. Q J
CLK K
Symbol of positive edge-triggered JK FF

23. JK Flip-Flops Q J CLK K Truth table
Symbol of positive edge-triggered JK FF Q J
CLK K
Toggle mode means when both JK are left high
the FF will change states for each clock pulse.

24. Waveform diagram for a JK flip-flop
JK Flip-Flops
J=0, K=1, Clk = and Q = 0
J=1, K=1, Clk = and Q toggles to 1
J=0, K=0, Clk = and Q remain at 0
J=1, K=1, Clk = and Q toggles to 1
All inputs are 0, and Q = 1 Q J
CLK K J K
Clk Q
Waveform diagram for a JK flip-flop
Click TO Continue

25. JK Flip-Flops
For the clocked flip-flops , the J,K, R, and S inputs have been referred to as control inputs. These inputs are called synchronous input, because their effect on the FF output is synchronized with the CLK input. Q J
CLK K

26. JK Flip-Flops
Asynchronous inputs Q J
CLK K PR
CLR
Asynchronous inputs operate independently of the synchronous inputs and clock input. These inputs can be used to set the FF to the 1 state or clear the FF to the 0 state at any time, regardless of the conditions at the other inputs.

27. JK Flip-Flops
Asynchronous inputs
Figure show J K FF has two asynchronous inputs PR and CLR. These are active-Low inputs as indicated by the bubbles on the FF symbol. When PR = CLR=1, the asynchronous inputs are inactive. Q J
CLK K PR
CLR

28. JK Flip-Flops When PR = CLR = 1, the asynchronous inputs are inactive.
PR = 0, and CLR = 1, Q = 1
CLR = 0 and PR = 1, Q = 0
PR = CLR = 0, this condition should not be used ( prohibited ) , as it can result in an ambiguous response. Q J
CLK K PR
CLR

29. D Flip-Flops The D flip-flop is also called Delay or Data flip-flop. Q
The D flip-flop has only one input.
It can be easily implemented from the RS or JK inputs as shown. Q J K D

30. Q follows D on the rising edge of the clock pulse.
D Flip-Flops
Edge-triggered D FF
Truth table Q D
CLK
D Clk Q
X no change
“ X ” indicates “don’t care”
Click TO Continue
Q follows D on the rising edge of the clock pulse.

31. Waveform diagram for a D flip-flop
D Flip-Flops
D =1, Clk = and Q = 1
D = 0, Clk = and Q = 0
D = 0, Clk = and Q = 0
D = 1, Clk = and Q = 1
Initaily Q = 1 Q D
CLK D
Clk Q
Waveform diagram for a D flip-flop
Click TO Continue

32. Q follows D when the FF is enabled; i.e. when EN = 1
D Flip-Flops
Level-triggered D FF
Truth table D EN Q
D EN Q
X no change
Q follows D when the FF is enabled; i.e. when EN = 1

33. Waveform diagram for a D flip-flop
D Flip-Flops
D =1, EN = 0 and Q = 0
D =1, EN = 1 and Q = 1
D =0, EN = 1 and Q = 0
D = 1, EN = 1 and Q = 1
D = 0, EN = 0 and Q = 1
“Latched”
“Transparent”
Both D and EN inputs are 0, and Q = 0 Q D EN D EN Q
Waveform diagram for a D flip-flop
Click TO Continue

34. T Flip-Flops The T flip-flop is also called toggle flip-flop. Q J T K
It can be easily implemented by tying the JK inputs of the JK FF to high as shown. Q J T K
CLK
High

35. T Flip-Flops
Truth table
Qn Clk Qn+1 Q T

36. T Flip-Flops Q T fo = 1/2 fin fo : Output frequency at Q
Wave format T input
Wave format Q output
fo = 1/2 fin
fo : Output frequency at Q
fin : Input frequency at T

37. Q 1
When both RS inputs are at logic ‘ 0’, the output Q of the flip-flop is at
A) Set state.
B) Reset state. S R Q FF
NOR gate FF would not response to logic ‘0’
C) unchanged state.
D) prohibited state.

38. The flip-flop can be constructed by using
Q 2
The flip-flop can be constructed by using
A) AND gates
B) OR gates S R Q FF
NAND gate FF is an active low FF.
C) NAND gates
D) NOR gates

39. The following symbol shows
Q 3
The following symbol shows
A) An active high RS Flip- flop.flop
B) An active low RS Flip-flop. S R Q FF
C) An positive edge-trigger active low RS Flip-flop.
D) An negative edge-trigger active low RS Flip-flop.
A bubble at the clock input represent an negative edge-trigger FF.

40. Q 4
A negative-edge-triggered flip-flop transfers data from input to output on the
A) falling edge of the clock pulse
Negative edge-trigger also referred to falling edge-trigger FF.
B) leading edge of the clock pulse
C) positive level of the clock pulse.
D) zero level of the clock pulse.

41. JK flip-flop does not result in
Q 5
JK flip-flop does not result in
A) set state
B) hold state
C) toggle state
Prohibited state only happened in RS FF
D) prohibited state

42. Q 6
When both JK inputs of the flip-flop are at logic 1, the clock pulse will cause the flip-flop to
A) reset the Q output.
B) set the Q output.
C) hold the Q output.
When both JK FF inputs are at logic 1, the FF is said to be operated in toggle state.
D) toggle the Q output to the next logic level.

43. Which of the following sequence will reset the flip-flop?
A) J=K=1, PR=CLR=1, and CLK = Q J
CLK K PR
CLR
B) J=K=0, PR=CLR=1, and CLK=
C) J, K, and CLK = X, where PR = 1 and CLR = 0.
D) J, K, and CLk = X, where PR = 0 and CLR =1.
PR and CLR are asynchronous inputs, CLR=0 will reset the FF.

44. Q 8
Which of the following JK flip-flop’s mode is not an asynchronous operation?
A) Set
B) Clear
C) Toggle
Toggle operation only took place when the Ff is triggered .
D) Hold

45. Q 9
Refer to the figure shown; a clocked RS flip-flop had been converted to
A) D flip-flop
B) D latch S
CLK R Q
C) T flip-flop
By connecting an inverter between the RS inputs of the FF, a D FF is formed.
D) JK flip-flop

46. Q 10
Refer to the figure shown; for CLK frequency = 20 kHz the output frequency is
A) 0 Hz Q D
CLK
B) 10 kHz
D FF was wired as an frequency divider cct.,
the output frequency
= ½ clock frequency.
C) 20 kHz
D) 40 kHz