1. Enhancement of Burst Beacon Design for the IEEE 802.22.1 Standard
September 2006
doc.: IEEE /0128r1
Nov 2006
Enhancement of Burst Beacon Design for the IEEE Standard
Date:
Authors:
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Ed Callaway, Motorola

2. September 2006
doc.: IEEE /0128r1
Nov 2006
Abstract
We propose an enhanced burst beacon transmission for the IEEE Enhanced Detection of Part 74 Devices standard.
Ed Callaway, Motorola

3. Background IEEE 802.22.1 Standard Status
September 2006
doc.: IEEE /0128r1
Nov 2006
Background
IEEE Standard
Enhance harmful interference protection for low-power licensed as secondary devices operating in TV Broadcast Bands (under Title 47 of the Code of Federal Regulations (CFR) in the USA and equivalent devices in other regulatory domains)
Target technologies for signalling the presence of low-power licensed devices that different from the sensing and cognitive radio technologies that are being considered elsewhere in
Status
Motorola’s proposal has been selected as baseline in Sept. meeting
Samsung introduced I/Q transmission
Ed Callaway, Motorola

4. Baseline PHY Beacon design is critical in the 802.22.1
September 2006
doc.: IEEE /0128r1
Nov 2006
Baseline PHY
Beacon design is critical in the
Sending 50 bytes in 5 ms requires a data rate of 80 kb/s, or a bit length of 12.5 ms.
Available spectrum bandwidth (< 200 kHz)
Required sensitivity (as good as possible)
Path loss aside, a path of even 10 km has a propagation delay of 33 µs, so multipath is a significant issue.
Multipath mitigation methods, such as equalization and OFDM, add undesirable complexity
Ed Callaway, Motorola

5. Current Burst-Beacon Design
September 2006
doc.: IEEE /0128r1
Nov 2006
Current Burst-Beacon Design
s Frame period
Sync N
Sync
N-1 …
Sync 1
Sync
BEACON PSDU
Length
Rx period
ANP
Sync N …
BEACON: 51 bytes, ms
BURSTS: Each 24b, ms
15 bits
9 bits
SYNCHRONIZATION
INDEX
~2.497 ms
Symbol (bit) time is long enough (104 ms) to ameliorate multipath/sensitivity concerns.
Each bit is spread with an 8-chip PN sequence (augmented 7-chip m-sequence), with fchip = kchip/s (= ATSC / 140 and bandwidth < 200 kH)
From the index, the WRAN determines when the beacon will be sent, and schedules a receiving frame accordingly
Synchronization word is a 15-bit m-sequence and makes falsing on noise unlikely
9-bit index word sufficient for 512 bursts (Maximum of 382 bursts actually sent every s)
Ed Callaway, Motorola

6. Merits and Problems Merits Index / Beacon could be vulnerable
September 2006
doc.: IEEE /0128r1
Nov 2006
Merits and Problems
Merits
Fairly simple design w/ low complexity demodulator
Fast burst detection w/ index facilitating scheduling …
Index / Beacon could be vulnerable
Less protection
Bits are protected only by 8 chip spreading
Unbalanced error protection
Sync word is further protected by 15-bit sequence to minimize miss alarm rate
Get synced but w/ wrong index or beacon errors
Objective
Improve bit protection performance and keep most (if not all) merits
Ed Callaway, Motorola

7. Proposed Burst-Beacon Design
September 2006
doc.: IEEE /0128r1
Nov 2006
Proposed Burst-Beacon Design
0.508 s
Sync
Sync
Sync
Length
BEACON PSDU I … …
N-1
N-2 Q
BURSTS: Each 16 b ms
BEACON: 50 Octets, ms
SAME chip rate ( kcps) and bit rate ( kbps)
New burst duration (1.665 ms or 16 bit duration)
QPSK signaling
Well balanced error protection for Sync (minimal false alarm rate), Index, and Beacon
Beacons is sent every 0.5 s
Ed Callaway, Motorola

8. Burst Design Nov 2006 In-phase Quadrature
September 2006
doc.: IEEE /0128r1
Nov 2006
Burst Design
128 chips (16 x 8)
Synchronization sequence C0
In-phase
Index subsequence C1(n1)
Quadrature
Index subsequence C1(n2)
64 chips
64 chips
Index n (n = 0 … 255)
128-chip synchronization sequence C0
Augmented 127 chip m-sequence
Hierarchical sequences are possible for simpler implementation (say 16 x 8)
Other better sequences?
Index n represented by a 128-chip sequence (C1(n1) followed by C1(n2))
64-chip index subsequence C1(n1) or C1(n2)
Augmented 63 chip m-sequence
Hierarchical sequences are possible for simpler implementation (say 16 x 4)
SINGLE base Index sequence C1
Index n (up to 256) represented by 2 concatenated subsequences, each cyclic shifted version of a base sequence C1
Ed Callaway, Motorola

9. cyclic-shifted to left 64-chip C1(n1) or C1(n2) subsequence
September 2006
doc.: IEEE /0128r1
Nov 2006
Index Subsequence
Subsequence
No. (n1 or n2)
Index n in binary
(1st or 2nd 4 bits)
Chip #
cyclic-shifted to left
64-chip C1(n1) or C1(n2) subsequence
Base sequence C1=(c1 , c2 … c63, c64)
0000
c1 , c2 , c3 , c4 , c5 … … c60, c61, c62, c63, c64 1
0001 4
c5 , c6 , c7 , c8 , c9 … … c64, c1 , c2 , c3 , c4 2
0011 8
c9 , c10, c11, c12, c13 … … c4 , c5 , c6 , c7 , c8 3
0010 12
c13, c14, c15, c16, c17 … … c8 , c9 , c10, c11, c12
0110 16
c17, c18, c19, c20, c21 … … c12, c13 , c14, c15, c16 5
0111 20
c21, c22, c23, c24, c25 … … c16, c17 , c18, c19, c20 6
0101 24
c25, c26, c27, c28, c29 … … c20, c21 , c22, c23, c24 7
0100 28
c29, c30, c31, c32, c33 … … c24, c25, c26, c27, c28
1100 32
c33, c34, c35, c36, c37 … … c28, c29, c30, c31, c32 9
1101 36
c37, c38, c39, c40, c41 … … c32, c33, c34, c35, c36 10
1111 40
c41, c42, c43, c44, c45 … … c36, c37, c38, c39, c40 11
1110 44
c45, c46, c47, c48, c49 … … c40, c41, c42, c43, c44
1010 48
c49, c50, c51, c52, c53 … … c44, c45, c46, c47, c48 13
1011 52
c53, c54, c55, c56, c57 … … c48, c49, c50, c51, c52 14
1001 56
c57, c58, c59, c60, c61 … … c52, c53, c54, c55, c56 15
1000 60
c61, c62, c63, c64, c1 … … c56, c57, c58, c59, c60
Ed Callaway, Motorola

10. Beacon subsequence C2(m1) Beacon subsequence C2(m2)
September 2006
doc.: IEEE /0128r1
Nov 2006
Beacon Transmission
In-phase
( nil )
Beacon subsequence C2(m1)
Quadrature
Beacon subsequence C2(m2)
64 chips
64 chips
Each octet of PSDU
Quadrature transmission only
Since Sync is secured
Quadrature power can be boosted up 3db for better Beacon reception
64-chip index sequence C2(m1) or C2(m2)
64-chip index subsequence C2(m1) or C2(m2)
Augmented 63 chip m-sequence
Hierarchical sequence is possible for simpler implementation (say 16 x 4)
SINGLE base Beacon sequence C2
Index n (up to 256) represented by 2 concatenated subsequences, each cyclic shifted version of a base sequence C2
similar to Burst
Ed Callaway, Motorola

11. cyclic-shifted to left 64-chip C2(m1) or C2(m2) subsequence
September 2006
doc.: IEEE /0128r1
Nov 2006
Beacon Subsequence
Subsequence
No. (m1 or m2)
Octet in Beacon
(1st or 2nd 4 bits)
Chip #
cyclic-shifted to left
64-chip C2(m1) or C2(m2) subsequence
Base sequence C2=(d1 , d2 … d63, d64)
0000
d1 , d2 , d3 , d4 , d5 … … d60, d61, d62, d63, d64 1
0001 4
d5 , d6 , d7 , d8 , d9 … … d64, d1 , d2 , d3 , d4 2
0011 8
d9 , d10, d11, d12, d13 … … d4 , d5 , d6 , d7 , d8 3
0010 12
d13, d14, d15, d16, d17 … … d8 , d9 , d10, d11, d12
0110 16
d17, d18, d19, d20, d21 … … d12, d13 , d14, d15, d16 5
0111 20
d21, d22, d23, d24, d25 … … d16, d17 , d18, d19, d20 6
0101 24
d25, d26, d27, d28, d29 … … d20, d21 , d22, d23, d24 7
0100 28
d29, d30, d31, d32, d33 … … d24, d25, d26, d27, d28
1100 32
d33, d34, d35, d36, d37 … … d28, d29, d30, d31, d32 9
1101 36
d37, d38, d39, d40, d41 … … d32, d33, d34, d35, d36 10
1111 40
d41, d42, d43, d44, d45 … … d36, d37, d38, d39, d40 11
1110 44
d45, d46, d47, d48, d49 … … d40, d41, d42, d43, d44
1010 48
d49, d50, d51, d52, d53 … … d44, d45, d46, d47, d48 13
1011 52
d53, d54, d55, d56, d57 … … d48, d49, d50, d51, d52 14
1001 56
d57, d58, d59, d60, d61 … … d52, d53, d54, d55, d56 15
1000 60
d61, d62, d63, d64, d1 … … d56, d57, d58, d59, d60
similar to Burst
Ed Callaway, Motorola

12. Simulation Results AWGN channel
September 2006
doc.: IEEE /0128r1
Nov 2006
Simulation Results
AWGN channel
Perfect chip pulse synchronization (no over-sampling)
Simple bit synchronizer finds the largest correlation peak
Packet error rate (Index and PSDU) / Probability of Sync Error
Ed Callaway, Motorola

13. Simulation Results Nov 2006 September 2006 doc.: IEEE 802.22-06/0128r12 4 6 8 10 12 14 -5 -4 -3 -2 -1
Fa = 0.004
Fa = 0.025
Eb/No (dB)
Sync Error Prob. / Packet Error Rate
AWGN, >100,000 runs each
Sync (15x8chps)
Index (9 bit)
Beacon Frame (48 byte)
I-Sync (128chps,1/2 power)
Q-Index (1 byte, 1/2 power)
Q-Beacon (48 byte, full power)
Ed Callaway, Motorola

14. Summary Enhancement for Burst Beacon Transmission is proposed
September 2006
doc.: IEEE /0128r1
Nov 2006
Summary
Enhancement for Burst Beacon Transmission is proposed
QPSK signaling
In phase: One PN sequence for Sync
Quadrature: One 64-chip base subsequence each for Index and Beacon
Balanced and better error protection
Sync word: 128-chip sequence
Index / Beacon octet: 128-chip sequence
Comprises of two 64-chip subsequences
Each subsequence is cyclic shifted version of base sequence
Low complexity implementation
Ed Callaway, Motorola