1. CDR Project Summary and Issues
Paul Dauncey
Imperial College London
11 October 2002
Paul Dauncey - CDR Summary

2. Paul Dauncey - CDR Summary
Cost estimates
Readout boards
2 prototypes, 15 system and 5 spare production
Cost £2600/board = £59k
Trigger boards
1 prototype, 2 system and 1 spare production
Cost £1200/board = £5k
Test board
1 board = £3k
Infrastructure
NRA = £2k, cables = £3k
PC/disk = £12k, PCI-VME = £7k, VME crates = £10k
Total infrastructure = £34k
System total = £101k
FY02/03 = £20k, FY03/04 = £81k
11 October 2002
Paul Dauncey - CDR Summary

3. Readout board scheduleN D J F M A S
Prototype
Design
PDR
Layout and fabrication
VFE-PCB tests
Testing
Production
Redesign
FDR
11 October 2002
Paul Dauncey - CDR Summary

4. Trigger board scheduleN D J F M A S
Prototype
Design
PDR
Layout and fabrication
Testing
Production
Redesign
FDR
11 October 2002
Paul Dauncey - CDR Summary

5. Engineering and technical effort
Readout board: 18 months engineering design
3 months Manchester (Dave Mercer)
10 months Imperial (Dave Price, Osman Zorba)
5 months missing
Trigger and test boards: 6 months engineering design each
5 months UCL (Martin Postranecky, Matt Warren)
7 months missing
Layout and fabrication: 5 months technical
If approved, need missing effort from RAL ID
Engineering design: 12 months effort, from Jan 2003 to Mar 2004
One person at 0.8FTE, could be project lead engineer
Technical: 5 months effort, mid and late 2003
11 October 2002
Paul Dauncey - CDR Summary

6. Paul Dauncey - CDR Summary
Feasibility issues
Is project possible given within cost, schedule and effort?
Still possible to adjust (slightly) proposal figures for cost and effort
Schedule set by end date, which may move later
Is system able to meet requirements?
Will it run at anywhere near 1 kHz?
Will the noise be low enough?
Is it flexible enough to deal with HCAL options?
Is the system testable enough to debug the boards?
Configuration data all read/write
Configuration data readback on event data path
DAC internal loopback to ADC’s
Calibration circuit on VFE-PCB’s
Test board is “inverted readout board” to check all signals on cables
Is firmware feasible within time and components?
11 October 2002
Paul Dauncey - CDR Summary

7. Some remaining design choices
Chosen VME but VME data rate (~20 MBytes/s) is limit of readout speed; is PCI/PXI a better choice?
Pros: faster by factor 2-3, innovative, less expensive (?)
Cons: No experience, possible mix of PCI and VME in system
6U readout board very tight for space
Six IDC 40-pin connectors might not fit on front panel: use back? 9U?
Components might not fit on board: double sided? 9U?
Reduce to five cables per readout board? Needs 18 boards
How many cables per slave FPGA?
Two-to-one would increase I/O pins by 57 but halve number of FPGA’s
Should trigger or readout boards give event VME interrupts?
Single interrupt simpler but need to poll for sequence completion
Trigger board stand-alone or simple rider on readout board?
Rider would reduce cost, second slave trigger board would not be mounted
11 October 2002
Paul Dauncey - CDR Summary

8. Some unsolved problems
VFE-PCB “LVDS” problem
VFE chip has PMOS input stage; they want to run this 0V to –5V rather than +5V to 0V to reduce noise.
All “LVDS” signals then offset by –5V from standard; e.g. quiescent level at –3.8V rather than +1.2V
Should the VFE-PCB convert to standard level or readout board convert from offset level?
Use alternative signal: ECL?
Connector/cable set choice
VFE-PCB has 4.5mm thickness constraint on combined PCB/connector
Proposed SHL connector needs cables soldered, cannot be mounted two deep on front panel and has a maximum of 20 pins
Trigger specification: how much logic goes inside the board?
Overdesign to accommodate all possible combinations of external logic?
11 October 2002
Paul Dauncey - CDR Summary

9. We would like to hear your thoughts!
Proposal will be resubmitted on 18 Nov
Must specify total equipment cost and RAL ID effort
What are the main things we need to do/fix before then?
Cost?
Main cost is readout boards
How can we be sure 6U is sufficient?
Are fabrication and assembly costs reasonable?
Main component cost is ADC’s
How do we determine whether these are usable?
Effort?
Most effort goes into FPGA firmware
How do we determine if we have allowed sufficient effort for these designs?
Is there enough left over for the rest of the designs?
11 October 2002
Paul Dauncey - CDR Summary