1. Instruction System - Bit Manipulation Instruction
计算机学院 李征
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2. Bit Manipulation Instruction
(1) AND
(2) OR
(3) XOR
(4) NOT
(5) TEST
(6) SAL, SAR
(7) SHL, SHR
(8) ROL, ROR
(9) RCL, RCR

3. Logic Operation Instruction
(1) AND
(2) OR
(3) XOR
(4) NOT
(5) TEST

4. AND AND DEST，SRC DEST <=（DEST）∧（SRC）
DEST and SRC are restricted with principles of instruction with two operation data.

5. AND
Status Flags:
SF, ZF, and PF are the same as those in arithmetic instructions.
CF=OF=0 (Forced to be zero)
AF is uncertain. (has no valid meanings)

6. Uncertain Status Flags
When an instruction explains a flag as an uncertain flag,
this flag may be changed by the instruction.
However, this flag can not provide useful information for programmer.

7. AND Example: （AL）=00101101B （AH）=10010111B AND AL，AH 00101101∧

8. AND After execution: No change in AH; (AL) = 00000101B SF=0，ZF=0，PF=1
CF=OF=0（Forced to be 0）
AF is uncertain.

9. OR OR DEST，SRC DEST <=（DEST）∨（SRC）
DEST and SRC are restricted with principles of instruction with two operation data.

10. OR
Status Flags:
SF, ZF, and PF are the same as those in arithmetic instructions.
CF=OF=0 (Forced to be zero)
AF is uncertain. (has no valid meanings)

11. OR Example: （BL）=11100010B （BH）=00111011B OR BL，BH 11100010 ∨ 00111011∨

12. OR After execution: No change in BH; (BL) = 11111011B SF=1，ZF=0，PF=0
CF=OF=0（Forced to be 0）
AF is uncertain.

13. XOR XOR DEST，SRC DEST <=（DEST）⊕（SRC）
DEST and SRC are restricted with principles of instruction with two operation data.

14. XOR （DL）=11010011B （DH）=10100010B XOR DH，DL 11010011 ⊕ 10100010⊕

15. XOR After execution: No change in DH; (DL) = 01110001B SF=0，ZF=0，PF=1
CF=OF=0（Forced to be 0）
AF is uncertain.

16. AND, OR, XOR They have similar affection to status flags.
Pay attention to CF, OF, and AF.

17. 与、或、异或
ALU
目的地址
源地址 ＯＦ ＤＦ ＩＦ ＴＦ ＳＦ ＺＦ ＡＦ ＰＦ ＣＦ X

18. NOT
NOT DEST
DEST <= ⌉（DEST）
No status flags affected by NOT.

19. Example of Logic Operation
STC
OR AL，1
ADC AL，BL
When ‘ADC’ is executing, what is CF status?

20. Bit Manipulation Bit Extraction; Bit Clearing; Bit Setting;
Bit Inversion;

21. Bit Extraction Example: （AL）=10100011B AND AL, 0FH
After execution,（AL）= B
Immediate data is bit-extraction mask.

22. Bit Clearing Example: (AL) = 00001111 AND AL, 0FEH
After execution, (AL)=
Immediate data is a bit-clearing mask.

23. Bit Setting Example: （AL）=00001000B OR AL, 11H
After execution, (AL)= B
Immediate data is a bit-setting mask.

24. Bit Inversion Example: (AL) = 01110101B XOR AL, 00100010B
After execution, (AL) = B
Immediate data B is a bit-inversion mask.

25. Application of Bit Manipulation
Bit manipulation is important for interaction between CPU and interface.
Bit setting, clearing, and inversion are often used in control port modification.
Bit extraction is often used in analysis of status port.

26. Example of Bit Manipulation
Assume the 2nd bit of port 35h can control an LED status.
When we want to lighten this LED, we could use the following program clip.
IN AL, 35H
OR AL, 02H
OUT 35H, AL

27. Example of Bit Manipulation
Assume the 1st bit of port 34h can describe the CAPS-LOCK status of keyboard.
If we want to know current status of CAPS-LOCK, we could use the following program clip.
IN AL, 34H
AND AL, 01H
Program branch can realized by program transfer instructions.

28. Example of Bit Manipulation
Data Combination:
AND AL，0F0H
AND BL，0FH
OR AL，BL
This program clip can combine the 4 higher bits of AL and lower 4 lower bits of BL.

29. Example of Bit Manipulation
Enable TF flag: (There is no instruction can operate TF directly.)
PUSHF
POP AX
OR AX，100H
PUSH AX
POPF

30. TEST TEST DEST，SRC （DEST）∧（SRC）
TEST is the same as AND, but it does not preserve the result.

31. ALU 与
目的地址
源地址 ＯＦ ＤＦ ＩＦ ＴＦ ＳＦ ＺＦ ＡＦ ＰＦ ＣＦ X

32. TEST Test instruction is used as bit-extraction and testing operation.
Programmer can realize program branch or cycle structure based on bit-status concerned.
In general cases, programmer interests in ZF affected by TEST.

33. TEST Example: TEST AL，00000100B
Here, whether the result is zero is equal to whether the 3rd bit of AL is zero.
Programmer can check the 3rd bit of AL by ZF flag.

34. TEST Remember the example about CAPS-LOCK of keyboard?
TEST can check the bits of status port easily.
Interest Relation:
SUB and CMP
AND and TEST

35. Branch and Cycle Structure in Program
In most cases, branch and cycle structures in program are realized by CMP and TEST instruction.
Actually, these two instructions represent two classic branch types in programming.

36. Bit Shift Instruction (6) SAL, SAR (7) SHL, SHR (8) ROL, ROR
(9) RCL, RCR

37. Bit Shift Instruction General format: OPR DEST，COUNT
DEST can be 8-bit or 16-bit register or memory cell.
If COUNT=1, it can be represent as 1.
If COUNT>1, it must be represent as (CL).

38. SAL SAL DEST，COUNT Shift (DEST) leftwards for COUNT-bits.
Lowest lost bit is preserved in CF.
The empty bits are filled with 0.
The (DEST) is considered as signed data in SAL.

39. SAL Flags Affected: OF、SF、ZF、PF、CF 、AF AF is uncertain.
OF is valid only if COUNT=1.
CF is used to join long signed data shifting.
SF, ZF, PF, OF is the same as those in arithmetic operation instructions.

40. Example:
SAL AL，1
Before SAL：
After SAL：
OF = 1 1 1 1 CF AL

41. CF AL Example: MOV CL，3 SAL AL，CL Before SAL： After SAL：
OF is Invalid because CPU can not detect correct sign changing. 1 1 1 CF AL

42. SAR SAR DEST，COUNT Shift (DEST) rightwards for COUNT-bits.
Highest lost bit is preserved in CF.
The empty bits are filled with original sign of (DEST).
The (DEST) is considered as signed data in SAR.

43. SAR Flags Affected: OF、SF、ZF、PF、CF 、AF AF is uncertain.
OF is valid only if COUNT=1. (However, is there overflow for SAR?)
CF is used to join long signed data shifting.
SF, ZF, PF, OF is the same as those in arithmetic operation instructions.

44. Example:
MOV CL，2
SAR AL，CL
Before SAR：
After SAR： 1 1 1 AL CF

45. Meaning of Arithmetic Shifting
SAL: For each bit shifted in signed data, the equal operation is multiplication with 2.
SAR: For each bit shifted in signed data, the equal operation is division with 2.
What is the minimal result of SAR operation?

46. Application Example
Example: Perform（AX）*3/2 without multiplication and division.
MOV DX，AX
SAL AX， ；（AX）*2
ADD AX，DX ；（AX）*3
SAR AX，1 ；（AX）*3/2

47. SHL SHL DEST，COUNT Shift (DEST) leftwards for COUNT-bits.
Lowest lost bit is preserved in CF.
The empty bits are filled with 0.
The (DEST) is considered as unsigned data in SHL.

48. SHL & SAL
For signed and unsigned data, their leftwards shifting are the same.
SHL and SAL correspond to the same machine instruction.
In debug, only SHL can be used.

49. SHR SHR DEST，COUNT Shift (DEST) rightwards for COUNT-bits.
Highest lost bit is preserved in CF.
The empty bits are filled with 0.
The (DEST) is considered as unsigned data in SHR.

50. Example:
MOV CL，2
SHR AL，CL
Before SHR：
After SHR： 1 1 1 AL CF

51. Meaning of Logic Shifting
SHL: For each bit shifted in unsigned data, the equal operation is multiplication with 2.
SHR: For each bit shifted in unsigned data, the equal operation is division with 2.
What is the minimal result of SHR operation?
OF is also affected in SHL and SHR. However, OF does not have valid meanings here.

52. ROL ROL DEST，COUNT Shift (DEST) leftwards for COUNT-bits.
Lowest lost bit is preserved in CF.
The empty bits are filled with lost bits.
Generally, the (DEST) is considered as bit manipulation mask.

53. ROL
Only CF and OF are affected.
OF is valid only if COUNT=1.

54. Example:
ROL AL，1
Before ROL：
After ROL：
OF=1 1 1 1 AL CF

55. ROR ROR DEST，COUNT Shift (DEST) rightwards for COUNT-bits.
Highest lost bit is preserved in CF.
The empty bits are filled with lost bits.
Generally, the (DEST) is considered as bit manipulation mask.

56. ROR
Only CF and OF are affected.
OF is valid only if COUNT=1.

57. AL CF Example: MOV CL，2 ROR AL，CL OF is invalid. Before ROR：
After ROR：
OF is invalid. 1 1 1 AL CF

58. Example for ROL or ROR Assume (AL) is the port status for testing.
Assume (CL) is the bit number for testing.
TESTSTATUS PROC
PUSH BX
MOV BL, 01H
ROL BL, CL
TEST AL, BL
POP BX
RET
TESTSTATUS ENDP

59. RCL
RCL DEST，COUNT
Consider CF as the highest bit of (DEST), and Shift (DEST) leftwards for COUNT-bits.
The empty bits are filled with lost bits which includes original CF.
Generally, RCL is used along with SHL or SAL for long data shifting.
Affected flags: CF, OF

60. Example:
RCL AL，1
Before RCL：
After RCL：
OF=1 1 1 1 CF AL

61. RCR
RCR DEST，COUNT
Consider CF as the Lowest bit of (DEST), and shift (DEST) rightwards for COUNT-bits.
The empty bits are filled with lost bits which includes original CF.
Generally, RCR is used along with SHR or SAR for long data shifting.
Affected flags: CF, OF

62. AL CF Example: MOV CL，2 RCR AL，CL OF is invalid. Before RCR：
After RCR：
OF is invalid. 1 1 1 AL CF

63. Long signed data shifting
Left shift: SAL and RCL
Overflow judgment: OF of the final shifting
Right shift: SAR and RCR (no overflow)

64. Long unsigned data shifting
Left shift: SHL and RCL
Overflow judgment: CF of the final shifting
Right shift: SHR and RCR (no overflow)

65. Long data rightwards shifting：
highest：
lowest：

66. Long data leftwards shifting：
Lowest
Highest

67. Long data shifting
If COUNT>1 in long data shifting, shifting must be performed bit by bit.
Why?
1) CF can only preserve one lost bit.
2) OF is invalid for multiple bit shifting.

68. Long data shifting
Example: A 48-bit unsigned data is preserved in word cell M+4, M+2, and M. Divide this long data by 2.
SHR M+4，1
RCR M+2，1
RCR M，1