1. DR S. & S.S. GHANDHY ENGINEENRING COLLEGE
Digital Electronics
Sub code:

2. Topic: Flip Flop, Counters, Register
NAME ENROLL NO
PIPALIYA RINKAL G CHOTALIYA NISHA J MODI JAINISA H MODI SEJAL P PATEL MEGHA J

3. Clock Signal Sequential logic circuits have memory
Output is a function of input and present state
Sequential circuits are synchronized by a periodic “clock” signal

4. FF vs. Latch
Latches and flip-flops (FFs) are the basic building blocks of sequential circuits.
latch: bistable memory device with level sensitive triggering (no clock), watches all of its inputs continuously and changes its outputs, independent of a clocking signal.
flip-flop: bistable memory device with edge-triggering (with clock), samples its inputs, and changes its output only at times determined by a clocking signal.

5. Flip Flop A basic sequential circuit is a flip-flop
Flip-flop has two stable states of complementary output values

6. SR Flip Flop

7. Clocked SR Flip Flop Circuit
Clock controlled flip-flop changes its state
only when the clock C is high

8. Positive Edge Triggered Flip Flop
Positive-edge triggered flip-flop changes only
on the rising edge of the clock C

9. J-K flip-flops

10. Negative Edge Triggered JK Flip Flop

11. T (toggle) flip-flops
A T FF changes state on every tick of the clock. (be toggled on every tick)
Q has precisely half the frequency of the T.
Important for counters
Positive-edge-triggered T FF

12. Asynchronous Counters
Up counter using T flip-flops
Count clock pulses
Q0 toggles on every 0  1 clock edge
Q1 toggles on every 1  0 transition of Q0
Q2 toggles on every 1  0 transition of Q1 T Q
Clock 1 2
MSB of count

13. Asynchronous Modulo 8 Up Counter
This counter counts 000  001  …  111  000
Assumes output is in order Q2 Q1 Q0
Modulo 8 up counter
The lower order flip-flop is synchronized to the Clock
All other flip-flops are not – asynchronous
Also called ripple counter T Q
Clock 1 2

14. Asynchronous Modulo 8 Down Counter
To count 111  110  …  001  000  111 T Q
Clock 1 2
Clock Q 1 2
Count 7 6 5 4 3

15. Synchronous Counters
Asynchronous counters are slow due to propagation delays
Synchronous counters share the clock among all flip-flops
clock cycle Q2 Q1 Q0 1 2 3 4 5 6 7 8
T0 = always toggle T1 = Q toggle when Q0 = 1 T2 = Q1Q toggle when Q1Q0 = 1 T3 = Q2Q1Q0 toggle when Q2Q1Q0 = 1 …

16. Waveform for Mod 16 Up CounterQ
Clock 1 2 3
Clock Q 1 2
Count 3 5 9 12 14 4 6 8 7 10 11 13 15

17. Registers A flip-flop stores one bit of information
When you want to store n bits  register
n flip-flops used
Clock is shared by all so action is synchronous with clock edge
Some common register types
Simple register
Shift register
Parallel access shift register
Lots of counters: up counter, down counter, BCD counter, ring counter, Johnson counter

18. Shift Registers

19. Shift Registers

20. Simple 4 Bit Register A standard 4 bit register using D flip flopsQ 3 2 1
Clock
Parallel input
Parallel output D

21. THANK YOU…