Presentation is loading. Please wait.

Presentation is loading. Please wait.

Basics Of X86 Architecture

Published byKristian Tucker Modified over 6 years ago

Similar presentations

Presentation on theme: "Basics Of X86 Architecture"— Presentation transcript:

1 Basics Of X86 Architecture
1 Basics Of X86 Architecture Prathmesh Kallurkar Teaching Assistant, Computer Architecture (CSL211) Instructor : Dr. Smruti Sarangi

2 2 2 Key Points What is x86 ? Chronology Overview

3 3 Overview X86 is a series of instruction set architectures based on Intel 8086 CPU. Original ISA was 16 bit. Term x86 derived from the ISA names ending with "86". 32 and 64 -bit implementations are known as x86-32 and x86-64 respectively. X86 ISA is complex and requires complex decoders. Relatively uncommon in small and low-power applications in embedded market. Who uses it : Intel, AMD, VIA

4 Chronology (History : Boring Huh ..)
4 Chronology (History : Boring Huh ..) 8086: 16-bit, all internal registers 16 bits wide; no general purpose registers; ’78 adds 80-bit-wide stack, but no registers; ’80 80286: adds elaborate protection model; ’82 new addressing modes; adds paging; ’85

5 Chronology (Contd.) MMX: + 57 instructions for multimedia; ‘97
AMD64 - First 64-bit CPU in x86 family, 2003 2006: Core 2 Multicore, SSE4 2008: Atom Deep pipeline, very low power

6 Basic Properties Key Points Design of x86 What is CISC ? Pros and Cons

7 Design of X86 Primarily two-address architecture
7 Design of X86 Primarily two-address architecture ARM : add r1, r2, r3 -> r1 = r2 + r3 X86 : add rax, rbx -> rax += rab Fewer instruction vs Compact representation Assumption : Often true in C, C++ : x+=y Register Memory architecture Load-Store architecture : simple decoder and pipeline Only load/store access memory RM : ALU operation can involve a memory and register operand Add 12 (%rsp), rbx - Requires less registers Assumption : Most of the accesses on array variables

8 Design Of X86 (Contd..) Little endian
What about ARM ?? Java ?? Allow unaligned memory-address access for 16 and 32 bits. Advantages : Memory-intensive Problems : Performance. Assumption : Most compilers will access aligned content. Variable length operation : operand-size can be byte(8), word(16), double-word(32) or quad-word(64)

9 CISC vs RISC Philosophy
9 CISC vs RISC Philosophy Instruction length RISC – fixed instruction. Easy fetch CISC – Intelligent fetch. Optimized icache Memory architecture RISC – Load/Store Architecture CISC – Register Memory Architecture Type of instructions x86 – enter : push and set combined Intel – Keep main core RISC. Add additional complex decoder

10 1010 1010 Addressing Modes Key Points Quiet obvious, isn’t it

11 Register Set (Integer - GPR)
1111 1111 Register Set (Integer - GPR) Accumulator : Arithmetic operations, System call Base for address operations Counter : Loop, String operations IO operations

12 Floating Point Registers
1212 Floating Point Registers The FPU has 8 registers, st0 to st7, formed into a FP stack. Build in the processor and has access speed same as register Stack instruction format : Pop arg1. Pop arg2 Apply operation Push solution Problem : Low instruction level parallelism Intel’s answer : vector operations

13 Addressing Modes Direct : R1 <- R1 + M[1001]
1313 Addressing Modes Direct : R1 <- R1 + M[1001] Global variable. Static data C : x = global variable Register Deferred : R4 <- R4 + M[R1] Pointer C : a = *b Indexed : R3 <- R3 + M[R1+R2] Local variable Scaled : R1<-R1+M[100+R2+R3*d] Used to index arrays. May be applied to any base addressing mode in some machines.

14 Assembly Programming Key Points Function Prologue Epilogue Variables
1414 1414 Key Points Function Prologue Epilogue Variables Local variable Function Parameter Global variable Hello World !! Assembly Programming

15 Stack Convention Stack grows downwards Caller convention
1515 Stack Convention Stack grows downwards Caller convention Pass arguments on the stack Foo( arg1, arg2, arg3 ) Push arg3, arg2, arg1 Call callee Callee convention Maintain local variables on stack Int local1, local2 Sub esp, 08h

16 1616 Global Variable Function Prologue Local Variable Function Epilogue

17 1717 Manage recursion. Intelligent use of eax register

18 1818 Addressing mode for accessing Structure elements Looping

19 1919 References Patterson - Stacks, Frames, and Calling Conventions by David Kyle

Download ppt "Basics Of X86 Architecture"

Similar presentations

Review of the MIPS Instruction Set Architecture. RISC Instruction Set Basics All operations on data apply to data in registers and typically change the.

Review of the MIPS Instruction Set Architecture. RISC Instruction Set Basics All operations on data apply to data in registers and typically change the.
Chapter 3 Instruction Set Architecture Advanced Computer Architecture COE 501.

Chapter 3 Instruction Set Architecture Advanced Computer Architecture COE 501.
ISA Issues; Performance Considerations. Testing / System Verilog: ECE385.

ISA Issues; Performance Considerations. Testing / System Verilog: ECE385.
1 Lecture 3: Instruction Set Architecture ISA types, register usage, memory addressing, endian and alignment, quantitative evaluation.

1 Lecture 3: Instruction Set Architecture ISA types, register usage, memory addressing, endian and alignment, quantitative evaluation.
RISC / CISC Architecture By: Ramtin Raji Kermani Ramtin Raji Kermani Rayan Arasteh Rayan Arasteh An Introduction to Professor: Mr. Khayami Mr. Khayami.

RISC / CISC Architecture By: Ramtin Raji Kermani Ramtin Raji Kermani Rayan Arasteh Rayan Arasteh An Introduction to Professor: Mr. Khayami Mr. Khayami.
1 ECE462/562 ISA and Datapath Review Ali Akoglu. 2 Instruction Set Architecture A very important abstraction –interface between hardware and low-level.

1 ECE462/562 ISA and Datapath Review Ali Akoglu. 2 Instruction Set Architecture A very important abstraction –interface between hardware and low-level.
10/9: Lecture Topics Starting a Program Exercise 3.2 from H+P Review of Assembly Language RISC vs. CISC.

10/9: Lecture Topics Starting a Program Exercise 3.2 from H+P Review of Assembly Language RISC vs. CISC.
Pentium 4 and IA-32 ISA ELEC 5200/6200 Computer Architecture and Design, Fall 2006 Lectured by Dr. V. Agrawal Lectured by Dr. V. Agrawal Kyungseok Kim.

Pentium 4 and IA-32 ISA ELEC 5200/6200 Computer Architecture and Design, Fall 2006 Lectured by Dr. V. Agrawal Lectured by Dr. V. Agrawal Kyungseok Kim.
CSE378 ISA evolution1 Evolution of ISA’s ISA’s have changed over computer “generations”. A traditional way to look at ISA complexity encompasses: –Number.

CSE378 ISA evolution1 Evolution of ISA’s ISA’s have changed over computer “generations”. A traditional way to look at ISA complexity encompasses: –Number.
COMP3221: Microprocessors and Embedded Systems Lecture 2: Instruction Set Architecture (ISA) Lecturer: Hui Wu Session.

COMP3221: Microprocessors and Embedded Systems Lecture 2: Instruction Set Architecture (ISA) Lecturer: Hui Wu Session.
CS 536 Spring 20011 Code generation I Lecture 20.

CS 536 Spring Code generation I Lecture 20.
State Machines Timing Computer Bus Computer Performance Instruction Set Architectures RISC / CISC Machines.

State Machines Timing Computer Bus Computer Performance Instruction Set Architectures RISC / CISC Machines.
RISC. Rational Behind RISC Few of the complex instructions were used –data movement – 45% –ALU ops – 25% –branching – 30% Cheaper memory VLSI technology.

RISC. Rational Behind RISC Few of the complex instructions were used –data movement – 45% –ALU ops – 25% –branching – 30% Cheaper memory VLSI technology.
CIS 314 : Computer Organization Lecture 1 – Introduction.

CIS 314 : Computer Organization Lecture 1 – Introduction.
Linked Lists in MIPS Let’s see how singly linked lists are implemented in MIPS on MP2, we have a special type of doubly linked list Each node consists.

Linked Lists in MIPS Let’s see how singly linked lists are implemented in MIPS on MP2, we have a special type of doubly linked list Each node consists.
Classifying GPR Machines TypeNumber of Operands Memory Operands Examples Register- Register 30 SPARC, MIPS, etc. Register- Memory 21 Intel 80x86, Motorola.

Classifying GPR Machines TypeNumber of Operands Memory Operands Examples Register- Register 30 SPARC, MIPS, etc. Register- Memory 21 Intel 80x86, Motorola.
Memory/Storage Architecture Lab Computer Architecture MIPS Instruction Set Architecture.

Memory/Storage Architecture Lab Computer Architecture MIPS Instruction Set Architecture.
Chapter Six Sun SPARC Architecture. SPARC Processor The name SPARC stands for Scalable Processor Architecture SPARC architecture follows the RISC design.

Chapter Six Sun SPARC Architecture. SPARC Processor The name SPARC stands for Scalable Processor Architecture SPARC architecture follows the RISC design.
Differences in ISA Instruction length

Differences in ISA Instruction length
Oct. 25, 2000Systems Architecture I1 Systems Architecture I (CS 281-001) Lecture 9: Alternative Instruction Sets * Jeremy R. Johnson Wed. Oct. 25, 2000.

Oct. 25, 2000Systems Architecture I1 Systems Architecture I (CS ) Lecture 9: Alternative Instruction Sets * Jeremy R. Johnson Wed. Oct. 25, 2000.

Similar presentations

Ads by Google