1. 14-BIT, 125MHz ADC Module Pedestal Subtraction Mircea Bogdan
April 5, 2016

2. PS Block – Preliminary Simulation
Two consecutive samples above threshold – condition satisfied, data passed through.
Two consecutive samples above threshold – condition NOT satisfied, a constant value passed through.
How this PS works:
If the 64 samples meet conditions, they are sent out after 66 clocks
If they don’t meet conditions, a constant value of 1000 is sent out
In both cases, the load_N_sample pulse is sent out after 66 clocks
PS Block can be disabled: data sent out as is, with only 1-clock delay

3. PS Logic
Conversion Logic(CL) can be controlled for each channel with two VME bits:
if CL[1..0]=0 => all data go through with the 66 clocks delay;
if CL[1..0]=1 => 64 samples go through with a 66 clock delay, only if at least one sample is over threshold, else a constant value of 1000 goes through;
if CL[1..0]=2 => 64 samples go through with a 66 clock delay, only if at least two samples are over threshold, else a constant value of 1000 goes through;
if CL[1..0]=3 => 64 samples go through with a 66 clock delay, only if at least two successive samples are over threshold, else a constant value of 1000 goes through;
Notes:
The load_N_samples pulse has to be between 1 and 64 clocks long.
The PS Block will send it out as long as it is, but will always calculate and send out 64 samples, with a 66 clock delay.

4. PS – VME Register Map
register 31[5] = 0 => PS disabled: Data, load_N_samples, load_packet delayed by 1 clock; register 31[5] = 1 => PS enabled: Data, load_N_samples, load_packet delayed by 66 clocks;
registers 2,3,4,5,6,7,8,9 have the threshold and logic mode for each channel:
register2[13..0]=threshold for adc[13..0], register2[15..14]=Conversion Logic for adc[13..0]
register2[29..16]=threshold for adc[27..14], register2[31..30]=Conversion Logic for adc[27..14]
register3[13..0]=threshold for adc[41..28], register3[15..14]=Conversion Logic for adc[41..28]
register3[29..16]=threshold for adc[55..42], register3[31..30]=Conversion Logic for adc[55..42] etc.

5. PS Logic – FPGA Resources (First Draft)
Flow Status Successful - Tue Mar 29 16:29:
Quartus II 64-Bit Version 12.0 Build /31/2012 SJ Full Version
Revision Name ADC_125mhz
Top-level Entity Name ADC_125mhz
Family Stratix II
Device EP2S60F1020C5
Timing Models Final
Logic utilization 59 %
Combinational ALUTs 17,570 / 48,352 ( 36 % )
Dedicated logic registers 19,973 / 48,352 ( 41 % )
Total registers 20014
Total pins 474 / 719 ( 66 % )
Total virtual pins 0
Total block memory bits 1,860,912 / 2,544,192 ( 73 % )
DSP block 9-bit elements 68 / 288 ( 24 % )
Total PLLs 3 / 12 ( 25 % )
Total DLLs 0 / 2 ( 0 % )
Flow Status Successful - Thu Mar 31 09:57:
Quartus II 64-Bit Version 12.0 Build /31/2012 SJ Full Version
Revision Name ADC_125mhz
Top-level Entity Name ADC_125mhz
Family Stratix II
Device EP2S60F1020C5
Timing Models Final
Logic utilization 62 %
Combinational ALUTs 18,428 / 48,352 ( 38 % )
Dedicated logic registers 21,222 / 48,352 ( 44 % )
Total registers 21263
Total pins 474 / 719 ( 66 % )
Total virtual pins 0
Total block memory bits 1,875,608 / 2,544,192 ( 74 % )
DSP block 9-bit elements 68 / 288 ( 24 % )
Total PLLs 3 / 12 ( 25 % )
Total DLLs 0 / 2 ( 0 % )
FPGA Resources with no PS Block
FPGA Resources with PS Block