1. Next steps - with notes from during the meeting 24 March 2016
W. Fedorko, J. J. John, M. Warren

2. The work ahead List of main tasks:
(same as 17/03/16 but Phase 2 added)
List of main tasks:
Basic infrastructure / getting started
Phase 1 – on Nexys Video
Adapt the ABC130* star HDL code to the ABCN’
Adapt ITSDAQ firmware and software to read out the ABCN’
Creating a CHESS-2 data emulator
Phase 2 - running ABCN’ on one FPGA board and the DAQ on a 2nd FPGA board
Phase 3 – on HSIO-2 with CHESS-2 daughterboard
Port the ABCN’ to the HSIO-2
Commission/debug with CHESS-2
Phase 4 – on CMOS demonstrator module
Help specify the CMOS demonstrator module (FPGA aspects)
Port the ABCN’ to the FPGAs on the hybrid/PCB
Commission/debug ABCN’ running on the module
+ merge in finalised ABC130* interface (L0tag etc)

3. Basic infrastructure - 1
Hardware, source code and repository
Task
Who
Obtain Nexys Video board, -- Oxford has one, thanks to Peter and Bruce for the loan.
Test with current ITSDAQ firmware and software
After discussion (17/03): it is some work to get communications set up to a Nexys Video with ITSDAQ, so allow some time for this. The steps are:
need a PC with a second network interface – extra card or USB network interface
programme the ITSDAQ firmware for Nexys V into the EEPROM onboard
talk to it via the ITSDAQ software (get from SVN, compile with ROOT)
WireShark is useful for monitoring network activity
There is a pushbutton to send a packet out of the Nexys V to the PC
It would be useful if we could write a register to gain control of the LEDs, then write another register to set the LEDs (sanity check/reasssurance)
All sites
Set up repository for ABCN’ with current ABC130* code
Done: gitlab.cern.ch/ABCNPrime/, with 2 projects:
ABCNPrimeFPGAEmulator
Chess2FPGAEmulator
Wojtek

4. Basic infrastructure - 2
ABC130* learning/reference materials
Task
Who
Update ABC130* block diagram with bit widths (buses, memories)
In progress
Jaya John
Prepare or generate diagram of ABC130* codebase
Instead imported ABC130* code to ITSDAQ firmware base
Matt
Serial interface to use for the ABCN’
Decision: after discussion this week with Paul, we decided to use the ABC130 serial interface (L0/Cmd and R3/L1) for the ABCN’.
The advantages are:
The DAQ already exists: ITSDAQ firmware and software already work with the ABC130.
The ABC130 command decoder and related code blocks already exist.
A code block to control the CHESS-2 Data Emulator already exists: the TMU which sits on the L0/CMD bus but has a distinct chip ID so can be addressed separately from the ABCN’.
The ABC130 interface is stable, while the ABC130* is still evolving (L0Tag etc)
About R3 requests: the R3 request still exists for the ABC130* (--Paul)
Wojtek (with help from Matt and Jaya John)

5. Phase 1 – on Nexys Video Task Who Create a CHESS-2 data emulator (DEM)
Generate random hits on emulated strips
Process hits as CHESS-2 does, to output data in same format
Provide a control interface to DEM. It should look an ABC130 series of chip (“TMU”) – receive commands on the same serial line from the DAQ firmware.
We agreed to revisit who will do which Phase 1 tasks, when we are further with the basics.
Adapt the ABC130* star HDL code to the ABCN’
Adapt widths of FIFOs/memories
Look at intention of Cluster Finder, see what is applicable
Provide a ABC130 Command-to-SACI bridge, to control AMS-CHESS-2
Provide a ABC130 Command-to-SPI bridge, to control TJ-CHESS-2
Adapt ITSDAQ firmware and software to read out the ABCN’
Need to use current serial line protocols as working in the present ABC130 code see discussion though at the bottom of slide 4

6. Next meeting
Due to Easter, we will not meet next week (skipping Thursday 31st March).
Our next meeting will be Thursday 7th April at 15:30 CERN time.