1. RX Compare Match Timer (CMT)
Hello and welcome to this Renesas Interactive course that covers the RX Compare Match Timer
4/20/2011
Rev. 1.00
© 2011 Renesas Electronics America Inc. All rights reserved.
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2. Agenda
This course contains a description of specific features of the RX Compare Match Timer (CMT).
Contained in this Module
Block Diagram
Interrupt Generation
Usage Notes
This course covers specific features of the Compare Match Timer, or CMT, found on RX MCUs.
In this course we will cover the CMT’s block diagram, interrupts generation, and some helpful usage notes.
© 2011 Renesas Electronics America Inc. All rights reserved.

3. Block Diagram Peripheral Bus
This figure shows a block diagram of a typical CMT unit on an RX MCU. An RX MCU might have multiple CMT units. Note that a single CMT unit contains 2 CMT timer channels.
These channels share a single register CMSTR containing each channels’ start bits.
At the bottom right we see that the CMT sits on the peripheral bus \and that the clock used for driving the timer is generated from a prescaled peripheral clock ranging from divide by 8 to divide by 512.
The prescalar selection is determined by a field in the CMCR register.
The period of the timeout is controlled by resetting the 16-bit counter value CMCNT when it equals the value set in the compare register CMCOR.
When the counter is reset by the compare match value, an event CMI is sent to the interrupt control unit. This event can generate an interrupt or the interrupt request state can be polled by software. There is a separate CMI interrupt for each CMT channel.
Note that the CMT’s have no external pins associated with them…they are completely internal resources that are typically used to generate periodic RTOS pre-emptions, software timeout notifications, or to trigger a DMAC or DTC transfer.
Peripheral Bus
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4. Interrupt Generation
To understand the detailed timing of the interrupt generation, the timing of the counter CMCNT needs to be explained.
Once per prescalar countdown, a count clock is generated for one peripheral clock period. It is this count clock that causes the counter CMCNT to be incremented.
The compare match signal is generated when counter CMNT is incremented by the count clock after it has matched the compare match CMCOR register. The period of the interrupt signal is therefore CMCOR+1 cycles of the count clock.
On the peripheral clock edge after the compare match signal is generated, the counter is reset and the CMI signal is sent to the interrupt control unit.
The CMI signal can generate an interrupt to the CPU core, trigger a DTC or DMAC transfer or be polled by software…the particular behavior is controlled by the configuration of the interrupt control unit.
© 2011 Renesas Electronics America Inc. All rights reserved.

5. Writing to the Count Regsiter
Usage Notes
Enable the CMT Unit
Writing to the Count Regsiter
Initializing Compare Match and Count Register
On this slide we will cover some usage notes for the CMT peripheral.
First, the user should always remember to bring each unit of CMT that they are using out of the module stop state. This is done by clearing the bit in the module stop control registers that corresponds to the CMT unit you are using. Please refer to the Low Power Consumption section of your RX group’s hardware manual to see which bits should be cleared. If this bit is not cleared then the CMT peripheral will be disabled and its registers will not writable.
The second note has to do with writing to the count register CMCNT. When the timer is running, writing to the count register at the instant of a compare match event will be ignored, and the count will be cleared to zero. If writing to the count register occurs at the same time as a count clock is present, the newly written value will be used and the count clock will be ignored.
Finally writing the same value to count register CMCNT and the compare register CMCOR can result in an interrupt being generated if the CMIE interrupt enable bit is set…even if the timer not running.
Also writing the same value to both registers will cause the counter register to be reset to zero as the match has technically occurred.
© 2011 Renesas Electronics America Inc. All rights reserved.

6. Summary Block Diagram Interrupt Generation Usage Notes
Thanks for Viewing!
In summary, in this course we covered:
the block diagram of the RX's CMT peripheral,
Detailed information on the interrupt generation,
And usage notes to be aware of when using the CMT peripheral.
We would like to thank for viewing this course. You may consider viewing the RX Family Overview Course for more information on RX MCUs.
© 2011 Renesas Electronics America Inc. All rights reserved.

7. © 2011 Renesas Electronics America Inc. All rights reserved.
Thank You
© 2011 Renesas Electronics America Inc. All rights reserved.