1. RX Data Transfer Controller (DTC)
Hello and welcome to this Renesas Interactive module that provides an overview of the RX Data Transfer Controller
Ver. 1.00
© 2011 Renesas Electronics America Inc. All rights reserved.

2. Course Introduction Purpose
Provide details on the RX Data Transfer Controller (DTC)
Content
DTC Overview
Transfer Modes
Chained Transfers
Register Set Overview
DTC and Interrupts
Learning Time
15 Minutes
The purpose of this Renesas Interactive module is to give you a basic understanding of the RX Data Transfer Controller or DTC. For a general overview of data movement peripherals like DMA’s and DTC’s, please see the Data Movement Peripherals overview module.
This module provides:
+ An overview of the RX DT
+ A brief discussion of the transfer modes the DTC supports
+ A look at chained transfers
+ An overview of the DTC register set
+ and a short explanation of how the DTC works with the Interrupt Controller in the RX
+ This module should take about 15 minutes to complete. Let’s get started.
© 2011 Renesas Electronics America Inc. All rights reserved.

3. Data Transfer Controller (DTC)
Here is a diagram of the RX Data Transfer Controller, or DTC
+ The DTC sits on Internal Main bus 2, and can act as a master on this bus, giving the DTC access to on-chip RAM and flash as well as on-board peripherals.
+ The DTC is tightly coupled to the Interrupt Control Unit or ICU, allowing the ICU the trigger DTC transfers and the DTC to pass interrupts to the CPU core.
+ There are two sets of registers in the DTC. The shared mode, control and status registers are in the normal register I/O space and accessible by software.
+ A second set of registers are not directly accessible by software and are shared by all DTC transfer channels.
Let’s see how it all works.
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4. DTC Operation DTC Descriptors in RAM MRA MRB Reserved SAR DAR CRA CRB
DTCCR
DTCVBR
DTCADMOD
DTCST
DTCSTS
The DTC includes two sets of registers:
+ user accessible registers that can be read and written just like other special function registers
+ and a set of internal registers that cannot be accessed directly by software
+ The DTC initializes its internal registers by reading descriptors from RAM when the DTC is triggered.
+ Each descriptor is a copy of the internal register set, and a table in RAM contains one descriptor for each of the interrupt sources that can trigger the DTC.
+ When triggered, the DTC fetches the descriptor for the requesting source and copies it into the internal registers. It then performs the data movement from the source to the destination addresses according to the setup for that source.
+ During the transfer, the source, destination and count registers will be updated. Once the transfer is complete + the updated descriptor is copied back out to RAM. Because the descriptors reside in RAM and share a single set of internal registers, the DTC can support many virtual transfer channels. On the RX, there are over 100 channels supported, allowing most peripherals to trigger automated transfers of data.
User accessible
Internal register
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5. DTC Vector Table Setup DTC Descriptors DTC MRA MRB Reserved SAR DAR
CRA
CRB
DTC Vector Table
Descriptor 1 address
Descriptor 2 address
Descriptor 3 address
Descriptor n address
Descriptor 2
DTCCR
DTCVBR
DTCADMOD
DTCST
DTCSTS
Let’s take a look at how the DTC determines which transfer descriptor to use.
+ The DTC Vector Base Register , or DTCVBR, points to the DTC Vector Table.
+ When the DTC is triggered, it receives a vector number that is unique for each source capable of triggering the DTC. The vector number is used to index into the DTC Vector Table. This is a data structure that your code must provide. Each location in the DTC Vector Table is 4-bytes and contains pointer to a DTC descriptor located in RAM.
+ This scheme provides you great flexibility in how you setup descriptors, and allows for very powerful chained transfers as we’ll see in a bit.
Now let’s take a close look at the format of the descriptors and the other control registers in the DTC.
Descriptor n
User accessible
Internal register
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6. DTC Setup DTC Long-Address Mode Descriptors in RAM MRA MRB Reserved
SAR
DAR
CRA
CRB
MRA
MRB
Reserved
SAR
DAR
CRA
CRB
4 Long Words
DTCCR
DTCVBR
DTCADMOD
DTCST
DTCSTS
MRA
MRB
SAR
DAR
CRA
CRB
Short-address mode
The values in the User Accessible registers shown in green determine overall setup for the Data Transfer Controller.
+ As we just saw, the DTC Vector Base Register contains a pointer to the start of the DTC Vector Table, which in turn points to the descriptors in RAM.
+ The DTC Address Mode Register selects one of two formats for the descriptors: Long and short address modes.
+ In long address mode, shown here, the source & destination addresses are both full 32-bit addresses and allow access to the full 4 gigabyte RX address space.
+ Set the Address Mode register to a 1 to enable short-address mode. In this mode, the addresses are shortened to 24-bits and the address is extended by the value in bit 23. The DTC can access two 16 Megabyte spaces: the highest and lowest 16-megabytes in memory. This covers all on-chip memory and peripherals, but excludes external memory space. In this mode, while you can’t access external memory with the DTC, the memory requirements for the DTC descriptor table are reduced and the access time for each read and write of the descriptor is reduced.
+ With DTC Control Register, you can configure the DTC to skip the reading of the descriptor data from RAM if the vector that triggers the DTC is the same as the previous trigger. In this case, the last values will still be in the internal registers and some overhead can be reduced. There are special circumstances where the DTC will fetch the descriptor from RAM regardless of the setting in DTC Control Register – so check the hardware manual for details.
+ The final two registers, the DTC Start Register and the DTC Status Register are used to start and stop the DTC and to check on the status of transfers.
3 Long Words
User accessible
Internal register
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7. DTC Normal Transfer Mode
Data 1
Data 2
Data 3
Data 4
Data 5
Transfer source data area
Transfer destination data area
SAR
DAR
Data 1
Data 2
Data 3
Data 4
Data 5
One data per request (8/16/32-bit)
SAR/DAR contain source & destination
Increment/decrement/fixed
CRA: Transfer counter, decremented each transfer
Up to transfers
Can interrupt with each transfer or at end of all transfers
In normal mode, the DTC transfers a single data item each time the DTC is triggered. It can be triggered from a number of hardware sources or by a software request.
+ During each transfer, a single 8-, 16-, or 32-bit data item is transferred from the source address to the destination address.
+ Each time the DTC is triggered, another data item is transferred from source to destination
+ The source & destination address registers keep track of where to move the data from and to
+ The DTC can be configured to leave the source & destination addresses unchanged after a transfer, or to automatically increment or decrement one or both. Each address’ behavior can be configured independently allowing easy transfer to and from peripheral registers to memory buffers. These options can be set for each channel of DTC transfer in each channel’s descriptor.
+ The transfer counter is decremented after each transfer, counting down to zero. It is 16-bits wide, allowing over 60,000 transfers to take place before the CPU has to intervene. Setting the transfer counter to zero results in transfers.
+ Finally, the DTC can generate an interrupt to the CPU at the end of each transfer, or just a single interrupt at the end of all transfers. To restart the DTC after the end of the transfer, you’ll have to reset the source & destination addresses and the transfer counter.
© 2011 Renesas Electronics America Inc. All rights reserved.

8. DTC Repeat Transfer Mode
Data 1
Data 2
Data 3
Data 4
Source area
Destination area
SAR
DAR
Data 1
Data 2
Data 3
Data 4
Data 1
Data 2
Data 3
Data 4
One data per request (8/16/32-bit)
SAR/DAR contain source & destination
CRAH: Repeat area size (up to 256 data items)
CRAL: Transfer count, decremented each transfer
No interrupts!
The DTC also supports Repeat Transfer Mode. As with normal mode, the DTC transfers a single data item each time the DTC is triggered.
+ During each transfer, a single 8-, 16-, or 32-bit data item is transferred from the source address to the destination address.
+ Each time the DTC is triggered, a data item is transferred from source to destination
+ The source & destination address registers keep track of where to move the data from and to. As with normal mode, the DTC can be configured to automatically increment or decrement one or both addresses.
+ The source or the destination can be specified as the repeat area, and the size of the repeat area can be up to 256 data items. In this example, we’ll use the source as the repeat area and a repeat area size of 4.
+ At each trigger of the DTC, a data item is transferred and the transfer count is decremented.
+ Transfers continue until the end of the repeat area is reached. At this time, the address register for the repeat area is reset to its initial value. Since the source area is the repeat area in our example, the SAR register is reset to point to the start.
+ The other address register continues to be updated, incrementing, decrementing, or remaining constant according to its configuration.
+ Further triggers of the DTC continue to transfer data, one item at a time. The repeat area is reset at the end of each scan. The DTC continues to run in this mode until your code stops it.
© 2011 Renesas Electronics America Inc. All rights reserved.

9. DTC Block Transfer Mode
Source area
Destination area
SAR
DAR
Block n .
First block
First block
Block Area
One block per request
SAR/DAR contain source & destination (inc/dec)
CRAH: Block size (up to 255)
CRAL: Transfer count (copy of CRAH)
CRB: Block count, decremented after each block xfer (64K)
Can generate interrupt at end of each block or last block
In Block Transfer Mode, the DTC transfers an entire block of data from the source to the destination area
+ At each request, the DTC transfers a block of data. The data within the block can be 8-, 16-, or 32-bit values.
+ As with the other modes, the source & destination address registers keep track of where to move the data from and to. The updates to the source & destination addresses happen as each data item is moved during the block transfer, so if the source or destination address was set to increment, then at the end of the block transfer it will point to the first data item after the block.
+ The source or the destination can be specified as the block area, and the size of the block area can be up to 255 items. In this example, the destination is the block area and the block size is 3.
+ A transfer counter is used internally by the DTC as it transfers each block; initialize it to the block size.
+ A separate block count is decremented each time the DTC is triggered and a block is transferred. This register is 16 bits wide allowing over 60,000 blocks to be moved.
+ The address register of the block area resets to the start of the block area after each transfer. In this example, since the destination area is the block area, the DAR register is reset after each transfer.
+ When the block counter reaches zero, the transfer ends and an interrupt is generated to the CPU. An interrupt may also be generated at each block transfer.
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10. DTC Chained Transfers Data Area DTC Descriptors DTC Vector Table 0x01
Descriptor 1-A
0x0A
0x0B
0x0C
Descriptor 1 address
Descriptor 2 address
Descriptor 3 address
Descriptor n address
0x01
0x02
0x03
One of the most powerful features of the DTC is its ability to perform chained transfers.
+ We’ve already seen the flexibility the DTC offers by creating many virtual channels through the DTC Vector Table. Each vector represents an interrupt source and points to unique descriptor in RAM.
+ The descriptors, in turn, contain the source and destination address for the data transfer that happens automatically when the DTC is triggered.
+ Once triggered, the DTC copies data from the source to destination address without CPU intervention.
Chaining builds upon the flexibility of the DTC vector and descriptor setup by allowing the DTC to process two or more descriptors sequentially.
+ Chained descriptors must be placed in memory back-to-back.
+ The chained descriptor has its own source & destination address, and when this descriptor is run data is copied + from the source + to the destination.
+ Any number of descriptors can be chained together, allowing sophisticated data-gather and data-scatter applications to be built with the DTC.
+ When triggered, the DTC processes the first descriptor moving data accordingly, updating the source & destination registers, and then saving the updated descriptor.
+ It then processes the next descriptor in the chain, moving data from its source to destination. This continues down the chain of descriptors until the end of the chain.
+ Two different modes are supported for chaining: in continuous mode, control is passed to the next descriptor at each trigger.
+ Non-continuous mode is for use in normal and block modes. In this mode, the first descriptor runs to completion until is transfer or block count is zero, and then the next descriptor is run.
The conditions that specify when interrupts are or are not generated when using chained transfers are explained in the hardware manual. DTC Transfer Chaining is one of the most powerful data movement features of the RX.
Descriptor 2
0x0A
0x0B
0x0C
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11. DTC Registers Basic registers for all transfers
Source & Destination Registers (SAR/DAR)
Transfer Count Register (CRA)
Block Counter Register (CRB)
Mode & control registers
Interrupt & status registers
Registers from other RX subsystems
Interrupt Control Unit (ICU) registers
Peripheral registers
Now let’s look at the registers that control the function of the DTC
+ There are a core set of four registers that control the transfers. These are the source & destination address registers, and the transfer and block count registers. We’ll see more about these in a bit.
+ Mode & control registers setup the DTC controller
+ And interrupt & status registers allow you to monitor the completion of DTC transfers
+Finally, it’s important to note that you may need to set registers in the Interrupt Control Unit and any peripherals that you will use to trigger the DTC.
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12. DTC Register Set Symbol Register name Access size Function MRA
DTC mode register A
Descriptor 1
Mode
MRB
DTC mode register B
SAR
DTC source address register
Descriptor 1,2
Address
DAR
DTC destination address register
CRA
DTC transfer count register A
Count
CRB
DTC transfer count register B
DTCCR
DTC control register 8
Control/status
DTCVBR
DTC vector base register
32 3
DTCADMOD
DTC address mode register
DTCST
DTC module start register
DTCSTS
DTC status register 16
Here’s the DTC register set.
+ First, it’s important to note that some of these registers are not directly accessible by software, but reside in RAM as part of the descriptor for each DTC channel.
+ The balance of the register can be read and written by your code and are shared across all channels of the DTC.
The registers fall into a handful of functional groups.
+ The mode registers configure a DTC channel for normal, repeat, or block mode, the size of the data operands, how to update the source & destination addresses after each transfer, and other options.
+ The source & destination address registers specify the source & destination for the data.
+ During transfers, the two count registers CRA and CRB keep track of the number of transfers and blocks.
Now let’s look at the registers that are shared by all channels of the DTC.
+ The Vector Base register points to the start of the DTC vector table. Each entry in the table corresponds to an interrupt source that can trigger a DTC channel, and contains a 32-bit pointer to a DTC descriptor located in RAM for that channel. It’s very important to note that the DTC vector base register’s least significant 12-bits must be zero; so be very careful where and how you locate the table.
+ The address mode register selects between full-address mode and short-address mode for the source & destination addresses. As we saw earlier, this register determines the format of the descriptor in RAM.
+ The remaining control and status registers control starting & stopping of the DTC.
Notes
1 These registers are not directly accessible, but are part of the descriptors in RAM.
2 SAR and DAR can be 32-bit or 24-bit depending on address mode register.
3 The 12 least-significant bits of the DTCVBR must be zero.
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13. DTC Interrupts Interrupts start DTC transfer
ICU: DTC Activation Enable Registers (DTCERn) (n=interrupt #)
DTCE = 1 routes interrupt signal to DTC rather than CPU
Not all sources can trigger DTC
DTCE bit cleared after last data or block transferred
Interrupts generated by DTC
Come in on original source’s vector (i.e. SCI1, TMR2)
After each transfer
At each transfer/block completion (normal & block modes)
Controlled by DISEL bit in CRB register
DTCERn (n=interrupt #)
--- b0
DTCE b7
Now let’s look at how the DTC works hand-in-hand with the RX Interrupt Control Unit, or ICU, to coordinate data movement.
+ DTC transfers are triggered in response to interrupt signals from the Interrupt Control Unit. These signals originate at on-chip peripherals and hardware interrupt pins.
+ In addition to the DTC registers, your code must configure registers in the ICU for the relevant interrupt sources. Each source that can trigger the DTC has a DTC Activation Enable Register. The registers are indexed by their corresponding interrupt vector number.
+ Setting the DTCE bit in this register routes the interrupt signal to the DTC instead of the CPU. Now when the interrupt fires, the DTC performs a data transfer.
+ Not every RX interrupt source can trigger the DTC, but the list of those that can is quite extensive – check the hardware manual for details.
+ After the last piece of data or last block has been transferred, the DTCE bit is cleared automatically and an interrupt is generated to the CPU. This allows the peripheral’s normal Interrupt Service Routine to take appropriate action. Subsequent triggers of the interrupt source will be routed to the CPU until the DTCE bit is set again.
+ Now let’s see what kind of interrupts can be generated by the DTC
+ First, it’s important to note that any interrupts generated by the DTC come in to the CPU on the triggering source’s vector. So if timer channel 2 triggered the DTC, the interrupt out of the DTC to the CPU will be on timer channel 2’s vector.
+ The DTC can be set to generate an interrupt at the end of each individual transfer
+ or at the completion of all the transfers or blocks for a given descriptor when the count registers change from 1 to zero.
+ This behavior is controlled by the DISEL bit in Control Register B of the descriptor.
By carefully configuring the DTC and the ICU, a significant amount of data movement can be set to run without any CPU overhead, freeing the CPU for other tasks.
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14. Summary DTC Overview Transfer Modes Chained Transfers Register Set
Normal
Repeat
Block
Chained Transfers
Register Set
DTC Interrupts
Into DTC to start transfers
Out of DTC to indicate status
Thank you!
This concludes this Renesas Interactive module.
In this session you’ve learned about
+ the RX Data Transfer Controller,
+ the three transfer modes it supports,
+ chained transfers,
+ the register set that controls the DTC,
+ and how to use the Interrupt Control unit to provide triggers to the DTC, as well as interrupts the DTC can send to the ICU.
+ Thanks for watching!
© 2011 Renesas Electronics America Inc. All rights reserved.