1. ENG6530 Reconfigurable Computing Systems
Assignment #1: bit Ripple Carry Adder Design
ENG6530: Assignment #1

2. Lab Objectives
Design a 4-bit Ripple Carry Adder using hierarchy (Half Adder, Full Adder, then 4-bit adder)
Supply the operands via Read Only Memory (ROM)
Display Results on 7-Segment Display
ENG6530: Assignment #1

3. Half Adder (One bit adder)
S = XY’ + X’Y
= X  Y
C = X.Y

4. Full Adder Three inputs: Two outputs: Implementation? X YZ
Cout S
Three inputs: X Y
Third is Cin  Z
Two outputs:
Sum
Cout
Implementation?

5. Straight Forward Implementation:
K Map for S S Z
What is this?

6. Straight Forward Implementation:
K Map for C X Y C X Z Y Z

7. Implementation Issues
If we try to implement the Optimized Boolean functions directly we will need how many gates?
Seven AND gates and two OR Gates!!
Can we do better?
YES!!
Share Logic
Hierarchical Design.

8. Any Alternatives?
Try to make use of hierarchy to design a 1-bit full adder from two half adders.
Also, try to share logic between the Sum output and Carry output.
Full Adder
S = X  Y  Z
C = XY + XZ + YZ
Half Adder
S = X  Y
C = XY

9. A Different Way to Represent C
XYZ YZ 00 01 11 10 X 1 1 XY
XYZ
C = XY + XYZ + XYZ
C = XY + Z (XY + XY)

10. Two Half Adders (and an OR)
How many Gates do we need?
Full Adder x y Z C S

11. Binary Ripple-Carry Adder
Straightforward – connect full adders
Carry-out to carry-in chain
C0 in case this is part of larger chain, maybe just set to zero

12. Hierarchical 4-Bit Adder
We can easily use hierarchy here
Design half adder
Use TWO half adders to create full adder
Use FOUR full adders to create 4-bit adder
VHDL CODE?

13. VHDL Half Adder (DATA FLOW)
entity half_adder is
port (x,y: in std_logic;
s,c: out std_logic);
end half_adder;
architecture dataflow of half_adder is
begin
s <= x xor y;
c <= x and y;
end dataflow

14. VHDL Full Adder (Structural)
entity full_adder is
port (x, y, z: in std_logic;
s, c: out std_logic);
end full_adder;
architecture struc_dataflow of full_adder is hs tc
component half_adder
port (x, y : in std_logic;
s, c : out std_logic);
end component;
signal hs, hc, tc: std_logic;
begin
HA1: half_adder
port map (x, y, hs, hc);
HA2: half_adder
port map (hs, z, s, tc);
c <= tc or hc;
end struc_dataflow hc

15. 4-bit Ripple Carry Adder
4-bit Adder: Operands
4-bit Ripple Carry Adder
SWITCHES
Selection
ROM #1
ROM #2
Address
ENG6530: Assignment #1

16. 7-Segment Display Truth table D a b c d e f g 0 1 1 1 1 1 1 0
seg7dec
D(3:0)
AtoG(6:0)
Truth table
D a b c d e f g
D a b c d e f g A b C d E F

17. 7-Segment Display library IEEE; use IEEE.STD_LOGIC_1164.all;
entity hex7seg is
port(
x : in STD_LOGIC_VECTOR(3 downto 0);
a_to_g : out STD_LOGIC_VECTOR(6 downto 0) );
end hex7seg;
architecture hex7seg of hex7segbis
begin
process(x)
case x is
when X"0" => a_to_g <= " "; --0
when X"1" => a_to_g <= " "; --1
when X"2" => a_to_g <= " "; --2
when X"3" => a_to_g <= " "; --3
when X"4" => a_to_g <= " "; --4
when X"5" => a_to_g <= " "; --5
when X"6" => a_to_g <= " "; --6
when X"7" => a_to_g <= " "; --7
when X"8" => a_to_g <= " "; --8
when X"9" => a_to_g <= " "; --9
when X"A" => a_to_g <= " "; --A
when X"B" => a_to_g <= " "; --b
when X"C" => a_to_g <= " "; --C
when X"D" => a_to_g <= " "; --d
when X"E" => a_to_g <= " "; --E
when others => a_to_g <= " "; --F
end case;
end process;

18. 7-Segment Display library IEEE; use IEEE.STD_LOGIC_1164.all;
entity hex7seg_top is
port(
sw : in STD_LOGIC_VECTOR(3 downto 0);
a_to_g : out STD_LOGIC_VECTOR(6 downto 0);
an : out STD_LOGIC_VECTOR(3 downto 0);
dp : out STD_LOGIC );
end seg7test;
architecture hex7seg_top of hex7seg_top is
component hex7seg is
x : in STD_LOGIC_VECTOR(3 downto 0);
a_to_g : out STD_LOGIC_VECTOR(6 downto 0)
end component;
begin
an <= "0000"; --all digits on
dp <= '1'; --dp off
D4: hex7seg port map
(x => sw,
a_to_g => a_to_g
end hex7seg_top;

19. 4-bit Adder: Display Results
ENG6530: Assignment #1