1. Synopsys PrimeTime

2. Introduction Static Timing Analysis tool
Static Timing Analysis : Determines whether the design works at the required speed.

3. PrimeTime ASIC design from Design Compiler PrimeTime
Timing performance and violation report or
Layout Verilog from IC Compiler
Design Constraints
Rise/Fall Time
Gate delay

4. PrimeTime Basic Flow set library path read the design
set search_path
set link_path
read the design
read_verilog
link library and the design
link
add design constraints
read_sdc
add constant value to input port (for timing simulation)
set_case_analysis
report
report_constraint
report_timing

5. Constraints File Example

6. Timing report

7. PrimeTime GUI

8. GUI - Timing Path

9. GUI – Timing Inspection

10. Tutorial Sources
/PrimeTime_Intro_to_STA/print_materials/PTISTA_lab1_flow.p df
%20Design%20Flow%20Tutorial.pdf