1. MDIO & PHY on AMIC110
April 27, 2017
Garrett Ding

2. Outline Overview PRU-ICSS MDIO PHY (TLK10xL, DP8x)
Enhanced link detection
Data Link (DL) status in EtherCAT

3. Overview

4. PRU-ICSS MDIO
The MII Management I/F module implements the serial management interface to interrogate and control two Ethernet PHYs simultaneously using a shared two-wire bus (MDIO_DATA, MDIO_CLK). Two user access registers to control and monitor up to two PHYs simultaneously.
The following tables show the read and write format of the 32-bit MII Management interface frames, respectively.

5. MDIO Registers
PRU_MDIO 0x4a332400

6. MDIO LINK register

7. MDIO PHYSEL register

8. TLK10xL PHY pin

9. PHY functional block diagram

10. DP83822 PHY pin

11. TLK10xL PHY
The TLK10xL pins fall into the following interface categories
• Serial Management Interface • Reset and Power Down
• MAC Data Interface • Bootstrap Configuration Inputs
• Clock Interface • 10/100Mbs PMD Interface
• LED Interface • Special Connect Pins
• Power and Ground pins

12. PHY Bootstrap Configuration
Bootstrap configuration is a convenient way to configure the TLK10xL into specific modes of operation.

13. PHY Address
The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin. Each TLK10x or port sharing an MDIO bus in a system must have a unique physical address. With 5 address input pins, the TLK10x can support PHY Address values 0 (<00000>) through 31 (<11111>). The address-pin states are latched into an internal register at device power-up and hardware reset. Because all the PHYAD[4:0] pins have weak internal pull-down/up resistors, the default setting for the PHY address is (0x01h).

14. PHY Address
An example of a PHYAD connection to external components. In this example, the
PHYAD configuration results in address (0x03h).

15. Auto-Negotiation
The TLK10x device auto-negotiates to operate in 10Base-T or 100Base-TX. With Auto-Negotiation enabled, the TLK10x negotiates with the link partner to determine the speed and duplex mode.
Auto-Negotiation advertises ANEN, 100BT by default. Full-Duplex or Half- Duplex configuration is available through the AN_0 bit. Internal register access configures the device for a specific mode.

16. Auto-MDIX
The TLK10x device automatically determines whether or not it needs to cross over between pairs, eliminating the requirement for an external crossover cable. If the TLK10x interoperates with a device that implements MDI/MDIX crossover, a random algorithm as described in IEEE determines which device performs the crossover.

17. LED Interface
By default, the TLK10xL supports one light emitting diode (LED) - LINK_LED, pin 17. In addition, the TLK10xL supports by register access a multi-configurable LED (MLED). The MLED is not activated by default, but by register access it can be routed through either pin 17 (allowing more configuration options for pin 17), or pin 29 supporting two simultaneous LEDs (LED_LINK on pin 17 & MLED on pin 29). When MLED is routed to the COL pin (pin 29) the COL functionality is disabled.
By default the TLK10xL is pin compatible to the TLK105, and the default LED output is LED_LINk on pin 17. The LED can be controlled by configuration pin and internal register bits. Bit 5 of the PHY Control register (PHYCR) selects the LED mode as described in Table 7-4.

18. Link Down Functionality
The TLK10xL includes advanced link-down capabilities that support various real-time applications. The link-down mechanism of the TLK10xL is configurable and includes enhanced modes that allow extremely fast reaction times to link-drops. the TLK10xL link loss mechanism is based on a time window search period, in which the signal behavior is monitored. The T1 window is set by default to reduce typical link-drops to less than 1ms. The TLK10xL supports enhanced modes that shorten the window called Fast Link Down mode. In this mode, which can be configured in Control Register 3 (CR3), address 0x000B, bits 3:0, the T1 window is shortened significantly, in most cases less than 10μs. In this period of time there are several criteria allowed to generate link loss event and drop the link.

19. Basic Mode Control Register (BMCR)

20. Basic Mode Control Register (BMCR)

21. LED Control Register (LEDCR)

22. PHYCR register

23. Multi LED Control register (MLEDCR)

24. LED on TLK10x vs. DP8x LedConfig PHYCR_REG 0x19 set to 0 or one PHYCR
(1u<<5)
LED_0 only
LedBlinkConfig
LEDCR_REG
0x18
blink number
LEDCR
LED_0 only blink and polarity
LEDCFG1
0x0460
LED_1 functions
IOCTRL
0x0462
LED_1 control
LEDCFG2
0x0469
LED_1 config

25. DP8x LED

26. LED_0, LED_1 on DP8x

27. Enhanced link detection
MDIOLINK Register is updated after a read of the Generic Status Register of a PHY. Typically the bit is set if the PHY with the corresponding address has link and the PHY acknowledges the read transaction. The bit is reset if the PHY indicates it does not have link or fails to acknowledge the read transaction. Writes to the register have no effect. In addition, the status of the two PHYs specified in the MDIOUSERPHYSELn registers can be determined using the MLINK input pins. This is determined by the LINKSEL bit in the MDIOUSERPHYSELn register.
The LINKSEL (Link status determination select) bit in MDIOUSERPHYSELn register determines link status using the MLINK pin by setting to 1. Default value is 0 which implies that the link status is determined by the MDIO state machine.

28. Enhanced link detection
pr1_mii0_rxlink/pr1_mii1_rxlink pin of PRU-ICSS, which connects to PHY LED_LINK/LED_SPEED pin is connected as MLINK signal to MDIO and in enhanced link detection mode MDIO directly uses MLINK signal to detect the link status from PHY. MDIO state machine based detection is very slow - slow serial link for messaging from MDIO controller to PHYs - this typically takes around us for PHYs. MLINK/mii_rxlink detection as fast as PHY can toggle this link – with special settings TI PHYs can detect link within 10us, depending on the PHY strap settings link polarity will be different for different boards and needs to adjusted per board by reading MDIOLINK register, also insure to set PHY LED_LINK/LED_SPEED mode as 'LINK_OK' in stead of 'RX/TX Activity' to prevent link detection failure from RX/TX activity.

29. DL status in EtherCAT
_Register_List
ESC DL status (0x4a31_0110)