1. SEQUENTIAL LOGIC -II

2. Latch versus Register Latch Register stores data when clock is low
stores data when clock rises D Q D Q
Clk
Clk
Clk
Clk D D Q Q

3. Writing into a Static Latch
Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states D
CLK D
Clk Q
Forcing the state
(can implement as NMOS-only)

4. Mux-Based Latches Negative latch (transparent when CLK= 0)
Positive latch
(transparent when CLK= 1)
CLK 1 D Q 1 D Q
CLK

5. Mux-Based Latch
(can implement as NMOS-only)

6. Mux-Based Latch (NMOS Only)
Non-overlapping clocks

7. Master-Slave (Edge-Triggered) Register
Two opposite latches trigger on edge
Also called master-slave latch pair

8. Master-Slave Register
Multiplexer-based latch pair

9. Clk-Q Delay 2.5 CLK 1.5 D t c  q(lh) t c  q(hl) Q 0.5 2 0.5 0.5 1
Volts c 
q(hl) Q
0.5 2
0.5
0.5 1
1.5 2
2.5
time, nsec

10. Setup Time –
I2 – T2
= 0.21 nsec
= 0.20 nsec

11. Reduced Clock Load Master-Slave Register

12. Avoiding Clock OverlapX
CLK
CLK Q A D B
CLK
CLK
(a) Schematic diagram
CLK
CLK
(b) Overlapping clock pairs

13. Static SR Latches ─ Cross-Coupled Pairs
NOR-based set-reset
Overpowering the Feedback Loop

14. Cross-Coupled NAND Added clock Cross-coupled NANDs
This is not used in datapaths any more, but is a basic building memory cell

15. Output voltage dependence on transistor width
Sizing Issues
Output voltage dependence on transistor width
Transient response

16. Storage Mechanisms
Static
Dynamic (charge-based)
CLK D Q
CLK

17. Making a Dynamic Latch Pseudo-Static

18. More Precise Setup Time

19. Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)

20. Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)

21. Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)

22. Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)

23. Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)

24. Setup/Hold Time Illustrations
Hold-1 case

25. Setup/Hold Time Illustrations
Hold-1 case

26. Setup/Hold Time Illustrations
Hold-1 case

27. Setup/Hold Time Illustrations
Hold-1 case

28. Setup/Hold Time Illustrations
Hold-1 case

29. Other Latches/Registers: C2MOS
“Keepers” can be added to make circuit pseudo-static

30. Insensitive to Clock-OverlapDD DD DD DD M M M M 2 6 2 6 M M 4 8 X X D Q D Q 1 M 1 M 3 7 M M M M 1 5 1 5
(a) (0-0) overlap
(b) (1-1) overlap

31. Other Latches/Registers: TSPC
Positive latch
(transparent when CLK= 1)
Negative latch
(transparent when CLK= 0)

32. Including Logic in TSPC
Example: logic inside the latch
AND latch

33. TSPC Register

34. Pulse-Triggered Latches An Alternative Approach
Ways to design an edge-triggered sequential cell:
Master-Slave Latches
Pulse-Triggered Latch L1 L2 L
Data
Data D Q D Q D Q
Clk
Clk
Clk
Clk
Clk

35. Pulsed Latches

36. Pulsed Latches
Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :

37. Pulsed Triggered Latches

38. Hybrid Latch-FF Timing

39. Sense-Amplifier Based Registers
Sense-amplifier-based flip-flop, DEC Alpha 21264, StrongARM 110
First stage is a sense amplifier, precharged to high, when Clk = 0
After rising edge of clock sense amplifier generates the pulse S or R
The pulse is captured S-R latch
Cross-coupled NAND has different delays of rising and falling edges

40. Pipelining
Pipelined
Reference

41. Latch-Based Pipeline

42. Multivibrator Circuits

43. Non-Bistable Sequential Circuits─ Schmitt Trigger
VTC with hysteresis
Restores signal slopes

44. Noise Suppression using Schmitt Trigger

45. CMOS Schmitt Trigger
Moves switching threshold
of the first inverter

46. Schmitt Trigger Simulated VTC
2.5
2.5
2.0
2.0 V
1.5 M +
1.5
(V)
(V) X x
1.0 V
1.0 V M - V k
= 1 k
= 3 k
= 2
0.5
0.5 k
= 4
0.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5 V
(V) V
(V) in in
Voltage-transfer characteristics with hysteresis.
The effect of varying the ratio of the
PMOS device M
. The width is k
* m. m 4

47. CMOS Schmitt Trigger (2)

48. Multivibrator Circuits

49. Transition-Triggered Monostable

50. Astable Multivibrators (Oscillators)

51. Voltage Controlled Oscillator (VCO)

52. Differential Delay Element and VCO
ctrl o 2 1 in
delay cell v 1 2 3 4 in 2
two stage VCO
0.5
0.0
1.0
1.5
2.0
2.5
3.0 2 V 1 3 4
time (ns)
3.5
simulated waveforms of 2-stage VCO