1. Digital Logic & Design
Dr. Waseem Ikram
Lecture No. 30

2. Recap Up/Down Counter IC 74HC190 Up/Down Counter Counter Decoding
3-bit down synchronous down counter
Up-down counter
IC 74HC190 Up/Down Counter
Counter Decoding
IC Counter Decoding
Digital Clock
Divide by 60 counter

3. Frequency Counter (fig 3a, 3b)
Counter Applications
Digital Counter
Divide by 60 counter timing diagram (fig 1a, 1b)
Hours Counter circuit (fig 2a)
Hours Counter timing diagram (fig 2b)
Frequency Counter (fig 3a, 3b)
Sampling intervals (fig 4)
Detailed Circuit diagram (fig 5a )
Timing diagram (fig 5b)

4. Timing diagram of the divide by 60 minutes/seconds counter

5. Timing diagram of the divide by 60 counter at time interval t56 to t64

6. Hours Counter Circuit

7. Hours Counter timing diagram

8. Frequency Counter Circuit

9. Timing diagram of the Frequency Counter Circuit

10. Cascaded Counter circuit for obtaining accurate sampling intervals

11. Detailed circuit diagram of a frequency counter

12. Timing diagram of the frequency counter circuit

13. Clocked Sequential State Machine (Mealy Machine)

14. Clocked Sequential State Machine (Moore Machine)

15. State diagram of a 3-bit Up-Counter

16. Design of Sync. Counters
Clocked Sequential circuits (fig 6a, 6b)
State diagram (fig 7)