1. DAC37J82 Settings
Kang Hsia

2. On-Chip PLL Configuration
DACCLKp/n at 240MHz – on-chip PLL reference
DAC output sampling clock at 1440MSPS (after interpolations)
PLL multiplier ratio = 6x
Desired VCO range for the PLL = 1440*3 = 4320MHz
Closest assured range = option 3
Pll_VCOTUNE = 2b’10 or 8.4mA to the VCO bias
Pll_VCO tested = d’44.
PLL_CP_adj can be set to 0.5mA initially. Further adjustment can be made to adjust the PLL control loop for optimal phase noise performance.

3. Mode 1: 2 lane (222), 180MSPS input
JESD = divide-by-8 from on-chip PLL clock of 1440MHz.
SERDES Reference = divide-by- 4 and multiply by 5 to generate 1800MHz clock.
On-chip PLL and Divider settings show on the left.

4. Mode 2: 4 lane (421), 180MSPS input
JESD = divide-by-16 from on- chip PLL clock of 1440MHz.
SERDES Reference = divide-by- 4 and multiply by 5 to generate 1800MHz clock.
On-chip PLL and Divider settings show on the left.

5. Mode 3: 4 lane (421), 720MSPS input
JESD = divide-by-4 from on-chip PLL clock of 1440MHz.
SERDES Reference = divide-by- 4 and multiply by 5 to generate 1800MHz clock.
On-chip PLL and Divider settings show on the left.