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CWRU EECS 317 EECS 317 CAD Computer Aided Design LECTURE 2: Delay models, std_ulogic and with-select-when Instructor: Francis G. Wolff

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Presentation on theme: "CWRU EECS 317 EECS 317 CAD Computer Aided Design LECTURE 2: Delay models, std_ulogic and with-select-when Instructor: Francis G. Wolff"— Presentation transcript:

1 CWRU EECS 317 EECS 317 CAD Computer Aided Design LECTURE 2: Delay models, std_ulogic and with-select-when Instructor: Francis G. Wolff wolff@eecs.cwru.edu Case Western Reserve University This presentation uses animation: please viewshow

2 CWRU EECS 317 Review: Full Adder: Truth Table

3 CWRU EECS 317 Review: Full Adder: Architecture ENTITY full_adder IS PORT (x, y, z:IN std_logic; Sum, Carry:OUT std_logic ); END full_adder; ARCHITECTURE full_adder_arch_1 OF full_adder IS BEGIN Sum <= ( ( x XOR y ) XOR z ); Carry <= (( x AND y ) OR (z AND (x AND y))); END full_adder_arch_1; ARCHITECTURE full_adder_arch_1 OF full_adder IS BEGIN Sum <= ( ( x XOR y ) XOR z ); Carry <= (( x AND y ) OR (z AND (x AND y))); END full_adder_arch_1; Optional Architecture END name; Entity Declaration Optional Entity END name; Architecture Declaration

4 CWRU EECS 317 Review: SIGNAL: Scheduled Event SIGNAL Like variables in a programming language such as C, signals can be assigned values, e.g. 0, 1 However, SIGNALs also have an associated time value A signal receives a value at a specific point in time and retains that value until it receives a new value at a future point in time (i.e. scheduled event) For example wave <= ‘0’, ‘1’ after 10 ns, ‘0’ after 15 ns, ‘1’ after 25 ns; The waveform of the signal is a sequence of values assigned to a signal over time

5 CWRU EECS 317 Review: Full Adder: Architecture with Delay ARCHITECTURE full_adder_arch_2 OF full_adder IS SIGNAL S1, S2, S3: std_logic; BEGIN s1 <= ( a XOR b ) after 15 ns; s2 <= ( c_in AND s1 ) after 5 ns; s3 <= ( a AND b ) after 5 ns; Sum <= ( s1 XOR c_in ) after 15 ns; Carry <= ( s2 OR s3 ) after 5 ns; END; Signals (like wires) are not PORTs they do not have direction (i.e. IN, OUT)

6 CWRU EECS 317 Signal order: ARCHITECTURE full_adder_arch_3 OF full_adder IS SIGNAL S1, S2, S3: std_logic; BEGIN Carry <= ( s2 OR s3 ) after 5 ns; Sum <= ( s1 XOR c_in ) after 15 ns; s3 <= ( a AND b ) after 5 ns; s2 <= ( c_in AND s1 ) after 5 ns; s1 <= ( a XOR b ) after 15 ns; END; ARCHITECTURE full_adder_arch_2 OF full_adder IS SIGNAL S1, S2, S3: std_logic; BEGIN s1 <= ( a XOR b ) after 15 ns; s2 <= ( c_in AND s1 ) after 5 ns; s3 <= ( a AND b ) after 5 ns; Sum <= ( s1 XOR c_in ) after 15 ns; Carry <= ( s2 OR s3 ) after 5 ns; END; No, this is not C! Net- lists have same beha vior & paral lel No, this is not C! Net- lists have same beha vior & paral lel Does it matter?No

7 CWRU EECS 317 Delta Delay

8 CWRU EECS 317 Delta Delay: Example using scheduling

9 CWRU EECS 317 Inertial Delay

10 CWRU EECS 317 Inverter model: lowpass filter (inertial) V out R1R1 C2C2 V in Short pulses = High frequency which get filtered out by cmos capacitance Long pulses = low frequency which pass through

11 CWRU EECS 317 Transport Delay

12 CWRU EECS 317 Inertial and Transport Delay Sig a b Inertial Delay is useful for modeling logic gates Transport Delay is useful for modeling data buses, networks

13 CWRU EECS 317 Combinatorial Logic Operators ANDz <= x AND y; NANDz <= NOT (x AND y); NORz <= NOT (x OR Y); ORz <= x OR y; NOTz <= NOT (x); z<= NOT x; XORz <= (x and NOT y) OR (NOT x AND y); z <= (x AND y) NOR (x NOR y); --AOI XNORz <= (x and y) OR (NOT x AND NOT y); z <= (x NAND y) NAND (x OR y); --OAI 2 2+2i 2i2i 2i2i 10 12 #Transistors Footnote: (i=#inputs) We are only referring to CMOS static transistor ASIC gate designs Exotic XOR designs can be done in 6 (J. W. Wang, IEEE J. Solid State Circuits, 29, July 1994)

14 CWRU EECS 317 Std_logic AND: Un-initialized value AND01U 0000 101U U0UU OR01U 001U 1111 UU1U 0 AND is 0 0 NAND is 1 1 OR is 1 1 NOR is 0 NOT01U 10U

15 CWRU EECS 317 SR Flip-Flop (Latch) R S Q Q NAND R S Q n+1 0 0 U 0 1 1 1 0 0 1 1 Q n R S Q Q NOR R S Q n+1 0 0 Q n 0 1 1 1 0 0 1 1 U Q <= R NOR NQ; NQ <= S NOR Q; Q <= R NAND NQ; NQ <= S NAND Q;

16 CWRU EECS 317 t 0 5 ns 10 ns 15 ns 20 ns 25 ns 30 ns 35 ns 40 ns R 1 1 0 0 0 0 1 1 1 Q U U U U 0 0 0 0 0 Q U U U 1 1 1 1 1 1 S 1 1 1 1 1 1 1 1 1 SR Flip-Flop (Latch) NAND R S Q n+1 0 0 U 0 1 1 1 0 0 1 1 Q n R S Q Q R(t) Q(t) S(t) Q(t) Q(t + 5ns) 5ns With Delay Example: R <= ‘1’, ‘0’ after 10ns, ‘1’ after 30ns; S <= ‘1’;

17 CWRU EECS 317 Std_logic AND: X Forcing Unknown Value AND0X1U 00000 X0XXU 10X1U U0UUU 0 AND is 0 0 NAND is 1 OR0X1U 00X1U XXX1U 11111 UUU1U 1 OR is 0 0 NOR is 1 NOT0X1U 1X0U

18 CWRU EECS 317 X The rising transition signal L W H 1 > 3.85 Volts Vcc=5.5 25°C 0 < 1.65 Volts Unknown 2.20 Volt gap

19 CWRU EECS 317 Modeling logic gate values: std_ulogic ‘1’,-- Forcing 1 ‘H’,-- Weak 1 ‘L’,-- Weak 0 ‘X’,-- Forcing Unknown: i.e. combining 0 and 1 TYPE std_ulogic IS ( -- Unresolved LOGIC ‘Z’,-- High Impedance (Tri-State) ‘0’,-- Forcing 0 ‘U’,-- Un-initialized ‘W’,-- Weak Unknown: i.e. combining H and L ‘-’,-- Don’t care ); Example: multiple drivers 011101111 1 X 0

20 CWRU EECS 317 Multiple output drivers: Resolution Function UX0LZWH 1- UUUUUUUUUU XUXXXXXXXX 0UX00000XX LUX0LLWW1X ZUX0LZWH1X WUX0WWWW1X HUX0WHWH1X 1UXX11111X -UXXXXXXXX Suppose that the first gate outputs a 1 the second gate outputs a 0 then the mult-driver output is X X: forcing unknown value by combining 1 and 0 together

21 CWRU EECS 317 Multiple output drivers: Resolution Function UX0LZWH 1- UUUUUUUUUU X XXXXXXXX 0 00000XX L LLWW1X Z ZWH1X W WW1X H H1X 1 1X - X Note the multi-driver resolution table is symmetrical Observe that 0 pulls down all weak signals to 0 H L => W

22 CWRU EECS 317 Resolution Function: std_logic buffer gate input: U0LWXZH 1- output: U00XXX11X 0 or L becomes 0 H or 1 becomes 1 Transition zone becomes X 1 H W, Z L 0 1 1 X 0 0 std_logic std_ulogic

23 CWRU EECS 317 Resolving input: std_logic AND GATE Process each input as an unresolved to resolved buffer. std_ulogic For example, let’s transform z <= ‘W’ AND ‘1’; std_logic Then process the gate as a standard logic gate { 0, X, 1, U } z <= ‘W’ AND ‘1’; -- convert std_ulogic ‘W’ to std_logic ‘X’ W 1 z <= ‘X’ AND ‘1’; -- now compute the std_logic AND X 1 z <= ‘X’; X

24 CWRU EECS 317 2-to-1 Multiplexor: with-select-when 0101 abab S Y abab Y S Y <= (a AND NOT s) OR (b AND s); WITH s SELECT Y <= a WHEN ‘0’, b WHEN ‘1’; WITH s SELECT Y <= a WHEN ‘0’, b WHEN OTHERS; or more general structural combinatorial logic behavioral Only values allowed 6 6 6 2 20 Transistors OTHERS includes 1,U,L,W,X,H,Z

25 CWRU EECS 317 4-to-1 Multiplexor: with-select-when Y <= sa OR sb OR sc OR sd; sa <= a AND ( NOT s(1) AND NOT s(0) ); sb <= b AND ( NOT s(1) AND s(0) ); sc <= c AND ( s(1) AND NOT s(0) ); sd <= d AND ( s(1) AND s(0) ); Y <= sa OR sb OR sc OR sd; sa <= a AND ( NOT s(1) AND NOT s(0) ); sb <= b AND ( NOT s(1) AND s(0) ); sc <= c AND ( s(1) AND NOT s(0) ); sd <= d AND ( s(1) AND s(0) ); WITH s SELECT Y <=a WHEN “00”, b WHEN “01”, c WHEN “10”, d WHEN OTHERS; abcdabcd S Y 00 01 10 11 As the complexity of the combinatorial logic grows, the SELECT statement, simplifies logic design but at a loss of structural information Structural Combinatorial logic behavioral Note the comma after WHEN

26 CWRU EECS 317 with-select-when: 2 to 4-line Decoder WITH S SELECT Y <= “1000” WHEN “11”, “0100” WHEN “10”, “0010” WHEN “01”, “0001” WHEN OTHERS; Y1Y1 Y0Y0 Y2Y2 Y3Y3 S0S0 S1S1 SIGNAL S: std_logic_vector(1 downto 0); SIGNAL Y: std_logic_vector(3 downto 0); SIGNAL S: std_logic_vector(1 downto 0); SIGNAL Y: std_logic_vector(3 downto 0); S1S1 S0S0 Y1Y1 Y0Y0 Y2Y2 Y3Y3 6 8 8 10 32 Transistors Replace this with a NOR, then 26 total transistors

27 CWRU EECS 317 Tri-State buffer oe y x ENTITY TriStateBuffer IS PORT(x:INstd_logic; y:OUTstd_logic; oe: INstd_logic ); END; ARCHITECTURE Buffer3 OF TriStateBuffer IS BEGIN WITH oe SELECT y <= x WHEN ‘1’, -- Enabled: y <= x; ‘Z’ WHEN OTHERS; -- Disabled: output a tri-state END;

28 CWRU EECS 317 Inverted Tri-State buffer oe y x ENTITY TriStateBufferNot IS PORT(x:INstd_logic; y:OUTstd_logic; oe: INstd_logic ); END; ARCHITECTURE Buffer3 OF TriStateBufferNot IS BEGIN WITH oe SELECT y <= NOT(x) WHEN ‘1’, -- Enabled: y <= Not(x); ‘Z’ WHEN OTHERS; -- Disabled END;

29 CWRU EECS 317 ROM: 4 byte Read Only Memory Y1Y1 Y0Y0 Y2Y2 Y3Y3 A0A0 A1A1 D0D0 OEOE 4 byte by 1 bit ROM ARRAY

30 CWRU EECS 317 ROM: 4 byte Read Only Memory ENTITY rom_4x1 IS PORT(A:IN std_logic_vector(1 downto 0); OE:IN std_logic; -- Tri-State Output D:OUT std_logic ); END; ARCHITECTURE rom_4x1_arch OF rom_4x1 IS SIGNAL ROMout: std_logic; BEGIN BufferOut: TriStateBuffer PORT MAP(ROMout, D, OE); WITH A SELECT ROMout <= ‘1’ WHEN “00”, ‘0’ WHEN “01”, ‘0’ WHEN “10”, ‘1’ WHEN “11”; Component declaration name Component Instance

31 CWRU EECS 317 Component Declaration/Instance relationship ARCHITECTURE rom_4x1_arch OF rom_4x1 IS COMPONENT TriStateBuffer PORT (x: IN std_logic; y: OUT std_logic, oe: IN std_logic); END COMPONENT; SIGNAL ROMout: std_logic; BEGIN BufferOut: TriStateBuffer PORT MAP(ROMout, D, OE); WITH A SELECT ROMout <= ‘1’ WHEN “00”, ‘0’ WHEN “01”, ‘0’ WHEN “10”, ‘1’ WHEN “11”; END; ARCHITECTURE rom_4x1_arch OF rom_4x1 IS COMPONENT TriStateBuffer PORT (x: IN std_logic; y: OUT std_logic, oe: IN std_logic); END COMPONENT; SIGNAL ROMout: std_logic; BEGIN BufferOut: TriStateBuffer PORT MAP(ROMout, D, OE); WITH A SELECT ROMout <= ‘1’ WHEN “00”, ‘0’ WHEN “01”, ‘0’ WHEN “10”, ‘1’ WHEN “11”; END; Colon (:) says make a Component Instance Component Declaration Component Instance Name: BufferOut

32 CWRU EECS 317 Component Port relationship BufferOut: TriStateBuffer PORT MAP(ROMout, D, OE); oe y x COMPONENT TriStateBuffer PORT (x: IN std_logic; y: OUT std_logic, oe: IN std_logic); END COMPONENT; COMPONENT TriStateBuffer PORT (x: IN std_logic; y: OUT std_logic, oe: IN std_logic); END COMPONENT; ENTITY rom_4x1 IS PORT(A:IN std_logic_vector(1 downto 0); OE:IN std_logic; -- Tri-State Output D:OUT std_logic ); END; OE  IN  oe  IN D  OUT  y  OUT

33 CWRU EECS 317 Assignment #2 (Part 1 of 3) 1) Assume each gate is 5 ns delay for the above circuit. (a) Write entity-architecture for a inertial model (b) Given the following waveform, draw, R, S, Q, NQ (inertial) R <= ‘1’, ‘0’ after 25 ns, ‘1’ after 30 ns, ‘1’ after 50 ns; S <= ‘0’, ‘1’ after 20 ns, ‘0’ after 35 ns, ‘1’ after 50 ns; (c) Repeat (b) but now assume each gate is 20 ns delay (d) Write entity-architecture for a transport model (e) Given the waveform in (b) draw, R, S, Q, NQ (transport)

34 CWRU EECS 317 Assignment #2 (Part 2 of 3) X F Y a (2) Given the above two tri-state buffers connected together ( assume transport model of 5ns per gate), draw X, Y, F, a, b, G for the following input waveforms: X <= ‘1’, ‘0’ after 10 ns, ‘X’ after 20 ns, ‘L’ after 30 ns, ‘1’ after 40 ns; Y <= ‘0’, ‘L’ after 10 ns, ‘W’ after 20 ns, ‘0’ after 30 ns, ‘Z’ after 40 ns; F <= ‘0’, ‘1’ after 10 ns, ‘0’ after 50 ns; G b

35 CWRU EECS 317 Assignment #2 (Part 3 of 3) 3) Write (no programming) a entity-architecture for a 1-bit ALU. The input will consist of x, y, Cin, f and the output will be S and Cout. Make components for 1-bit add/sub. The input function f (with-select) will enable the following operations: function fALU bit operation 000S = 0; Cout = 0 001S = x 010S = y; Cout =1; 011S = Cin; Cout = x 100S = x OR y; Cout=x; 101S = x AND y; Cout=x; 110(Cout, S) = x + y + Cin; (component) 111(Cout, S) = full subtractor (component) x ALU y C in f S C out

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