1. Erno david , Shuaib Ahmad Khan
I2C Interface Evaluation 1 2 3
N-1
Register
set
MiniPods (for eg)
I2C Slave
FPGA
I2C Master
Wishbone Interface
Addr
Data EN WR
CPU Or
NIOS2
(C code)
Jtag to
Avalon MM
(TCL Script
Processor
Wishbone Drive
S: I2C Addr+Wr
S: Reg Addr
S: Data
SCL
SDA
GBT-FPGA
Firmware
GBTx SCA
E-Link
GBTx ASIC
FLP
Optical
Fiber
HDLC
CRU(Lets say)
Erno david , Shuaib Ahmad Khan

2. Demo on Cyclone IV FPGA Cyclone IV FLP/CPU Or NIOS2 (C code) Jtag to
Avalon MM
(TCL Script)
SCL
I2C
Master S M
Qsys
Interconnect S
SDA M
MINIPODs for ARRIA10/
EEPROM for CycloneIV
PLL

3. QSYS Design

4. Test Results
DE0-Nano - Altera Cyclone IV FPGA

5. With Stratix V AMC 40

6. Further
Modified the design for Reflex A10 board.
But Remotely accessing the FPGA board failed (under observation)
Next steps
Testing the I2C scanner over the PCIe bus in Stratix
Investigating the idea how to do the I2C scanning with the SCA
To verify the I2C read/write in one slave fully