2. Asynchronous Inputs of a Flip-Flop
Lecture
Digital Systems
Asynchronous Inputs of a Flip-Flop
All inputs that we have been studying in all the flip-flops (D, S-R, J-K, and T) are synchronous inputs because their effect on the FF output is synchronized with the clock input.
Most clocked FFs also have asynchronous inputs that operate independently of the synchronous inputs and clock input.
These asynchronous inputs can be used to set the FF to 1 or 0, regardless of the conditions at the synchronous inputs

3. Asynchronous Inputs of a Flip-Flop
Lecture
Digital Systems
Asynchronous Inputs of a Flip-Flop

4. Lecture
Digital Systems
Summary Flip-flops
Flip-flops are powerful storage elements. They are constructed from gates and latches.
D flip-flop is the simplest and the most widely used type.
Multiple flip-flops allow for data storage. They are the basis of computer memory.
Furthermore, combination of sequential logic and combinatorial logic build computation circuit.

5. Flip-Flop Applications: Parallel Data Storage
Lecture
Digital Systems
Flip-Flop Applications: Parallel Data Storage
Common requirement in digital systems is to store several bits of data from parallel lines simultaneously in a group of flip-flops.
This group of four flip-flops is an example of a basic register used for data storage.
The clock inputs of the flip-flops are connected together. Positive edge-triggered flip-flops are used.

6. Flip-Flop Applications: Parallel Data Storage
Lecture
Digital Systems
Flip-Flop Applications: Parallel Data Storage

7. Flip-Flop Applications: Frequency Division
Lecture
Digital Systems
Flip-Flop Applications: Frequency Division
Another application of a flip-flop is dividing (reducing) the frequency of a periodic waveform.
D flip-flop or J-K flip-flop can be used, with the connection shown below.
Both flip-flops performs frequency division of 21.

8. Flip-Flop Applications: Frequency Division
Lecture
Digital Systems
Flip-Flop Applications: Frequency Division
Frequency division of 2n can be done by using n flip-flops connected in series.
Below, frequency of QB is ¼ frequency of the clock.

9. Flip-Flop Applications: Digital Counters
Lecture
Digital Systems
Flip-Flop Applications: Digital Counters
Asynchronous digital counter
Clock only connected to first FF  Ripple effect due to gate delay
0 0
0 1
1 1
QA QB

10. Flip-Flop Applications: Digital Counters
Lecture
Digital Systems
Flip-Flop Applications: Digital Counters
Another important application of flip-flops is in digital counters.
Digital counters not only count things. They are useful as frequency meters, parts of A/D converters, etc.
Negative edge-triggered J-K flip-flops are used for illustration.
Synchronous digital counter
Clock connected to every FF

11. Characteristic Equation
Lecture
Digital Systems
Summary Flip-flops
S-R flip-flop Note: all output changes are on clock edge only
Characteristic Table
Karnaugh Map for Qnext SR Q 00 01 11 10 1 X S R
Qnext Q 1 X
Characteristic Equation
State Diagram
Qnext = S + R’Q 1 X0 01 0X 10

12. Characteristic Equation
Lecture
Digital Systems
Summary Flip-flops
D flip-flop Note: all output changes are on clock edge only
Characteristic Table
Karnaugh Map for Qnext Q 1 D D
Qnext 1
Characteristic Equation
State Diagram
Qnext = D 1

13. Characteristic Equation
Lecture
Digital Systems
Summary Flip-flops
J-K flip-flop Note: all output changes are on clock edge only
Characteristic Table
Karnaugh Map for Qnext JK Q 00 01 11 10 1 J K
Qnext Q 1 Q’
Characteristic Equation
State Diagram
Qnext = JQ’ + K’Q
Qnext = JQ’ + K’Q + JK’ 1 X0 X1 0X 1X

14. Characteristic Equation
Lecture
Digital Systems
Summary Flip-flops
T flip-flop Note: all output changes are on clock edge only
Characteristic Table
Karnaugh Map for Qnext Q 1 T T
Qnext Q 1 Q’
Characteristic Equation
State Diagram
Qnext = TQ’ + T’Q
= T  Q 1

15. Sequential Circuits: Finite State Machine
Digital Systems
Section 11
Sequential Circuits: Finite State Machine

16. Lecture
Digital Systems
Finite State Machine
Finite State Machine (FSM) is an abstract machine that can be in exactly one of a finite number of states at any given time.
FSM can change from one state to another in response to some external inputs.
The change from one state to another is called transition.
FSM is defined by a list of its states, its initial state, and the conditions for each transition.
In general an FSM circuit has a set of primary inputs W, and produces a set of output Z. The output of the flip-flops are referred to as the state Q.
The combinational circuit provide the input signals to the flip-flops. The input to this combinational circuits are the primary inputs W and the present outputs of the flip-flops Q.

17. Finite State Machine FSM, Moore Type
Lecture
Digital Systems
Finite State Machine
FSM, Moore Type
Output Z depends only on the state of the circuit Q.
Combinational Logic Circuit W Z Q
Flip- Flops
Clock
FSM, Mealy Type
Output Q depends on the state of the circuit Q and the primary inputs W.
Combinational Logic Circuit W Z Q
Flip- Flops
Clock

18. State of Sequential Logic Circuit
Lecture
Digital Systems
State of Sequential Logic Circuit
In sequential logic circuit, memory elements such as flip-flops are used. The stored contents of these memory elements, at a given time, is referred to as the circuit’s state.
Since each flip-flop has only two possible states, 0 or 1, then a sequential circuit with N flip-flops will have a finite number of possible states, with the maximum number equals 2N.
The inputs and the current state will determine the next state and the output of a sequential logic circuit.
A sequential logic circuit can be represented by using a state table or a state diagram.

19. Lecture
Digital Systems
State Table
A state table of a sequential logic circuit lists all possible inputs for all possible states of the circuit, and how the circuit will move from one state to another.
The outputs, if any, may also be given in additional column.
Below is an example of a state table.
Input
Current State
Next State
Output Y1 Y0 1
All state transitions only occur during the active edge of the clock !

20. A state diagram without output
Lecture
Digital Systems
State Diagram
In a state diagram, a state is represented by a circle, and the transition between the states is represented by arrow/arc.
Every state is given name (S0, S1, ..., S23, etc.) or number (00, 01, ..., 101, etc.) inside the circle.
Every transition is given the corresponding input at the arrow/arc.
Possible inputs while at State 10
Transition to State 11 for input equals 1 10 1 11
Transition back to State 10 for input equals 0
State 10
State 11
A state diagram without output

21. State Diagram for Moore Type State Diagram for Mealy Type
Lecture
Digital Systems
State Diagram
For Moore Type machine, the output is given next to the state name or state number (inside the circle, separated by slash).
For Mealy Type machine, the output is given next to the input (at the arrow/arch, separated by slash).
Output equals 1 while and after transition from State 10 to State 11
Input / Output
10/0 1
11/1 10
1/1
0/0 11
State / Output
Output equals 0 while at State 10
State Diagram for Moore Type
State Diagram for Mealy Type

22. Example: State Diagram
Lecture
Digital Systems
Example: State Diagram
Draw the state diagram of a sequential logic circuit, with the following specifications:
The circuit has one input and one output.
The output is equal to 1 if during two consecutive clock cycles the input was equal to 1. Otherwise, the output is equal to zero.
The circuit will detect if an input signal was high for two consecutive clock pulse

23. Example: State Table to State Diagram
Lecture
Digital Systems
Example: State Table to State Diagram
Given the following state table, draw the state diagram.
Input
Current State
Next State
Output Y1 Y0 1 00
1/0
0/0 01 11 10
1/1
Mealy Type

24. Design of Sequential Logic Circuits
Lecture
Digital Systems
Design of Sequential Logic Circuits
Obtain the specification of the desired circuit.
Derive the states for the machine. Select a starting state. Then, consider all impacts of the inputs to the circuit. Create a state diagram.
Create a state table from the state diagram.
Determine the number of flip-flops needed.
Choose the type of flip-flops to be used in the circuit.
Derive the logic expressions to control the inputs to all flip-flops.
Derive the logic expressions for the outputs of the circuit.
Implement the circuit as indicated by the logic expressions.

25. Example: Counter Design
Lecture
Digital Systems
Example: Counter Design
Design a 2-bit counter that will count the output Y1Y0 as 00, 01, 10, 11, 00, 01, ... for every positive edge of the clock. If the input X is equal to 0, the count will stop, whereas if the input X is equal to 1, the count will proceed.
Perform the design by using two S-R flip-flops, with the output Y1 and Y0.
Input
Current State
Next State
FF1
FF0 X Y1 Y0 S1 R1 S0 R0 1
Input
Current State
Next State
FF1
FF0 X Y1 Y0 S1 R1 S0 R0 ? 1 Q
Qnext S R X 1
S-R FF Excitation table
State Table of the Counter
Use the excitation table of the S-R flip-flop to connect a state to next-state.

26. Example: Counter Design
Lecture
Digital Systems
Example: Counter Design
Y1Y0 X 00 01 11 10 1
Y1Y0 X 00 01 11 10 1
K-map for S1
K-map for S0
Y1Y0 X 00 01 11 10 1
Y1Y0 X 00 01 11 10 1
K-map for R1
K-map for R0
S1 = XY1’Y0
R1 = XY1Y0
S0 = XY0’
R0 = XY0
Find the equation for all the inputs of the flip-flops, to connect the counter’s input and the current state to the next-state.

27. Example: Counter Design
Lecture
Digital Systems
Example: Counter Design X S1 Q Q’
FF1 Y1 R1 S0 R0
FF0 Y0
Clock
Logic Diagram of the Counter
S1 = XY1’Y0 S0 = XY0’
R1 = XY1Y0 R0 = XY0
Realize the logic circuit, which consists of sequential logic components (flip- flops) and combinatorial logic components (AND gates).

28. Example: Sequential Circuit Design
Lecture
Digital Systems
Example: Sequential Circuit Design
Using J-K flip-flops, design the corresponding sequential logic circuit for this state diagram. The input is denoted by X 00 11 01 10 1
J1 = X J0 = Q1X’ K1 = Q0’X’ + Q0X K0 = Q1X A

29. Example: Vending Machine
Lecture
Digital Systems
Example: Vending Machine
A soft drink vending machine takes Rp5 and Rp2 banknotes only. The price of the drink is Rp6. When the sum of money input is more or equal to Rp6, the drink will be dispensed. However, the vending machine does give back any change.
Use a Mealy Model. Draw the state diagram and the state table for the vending machine.
Inputs
Output
State is given names S0,..., S3.
There are 2 inputs: A represents Rp5 input, B represents Rp2 input.
There is 1 output: 1 means a drink is dispensed, 0 means no drink is dispensed.
There are 4 states  we will need 2 flip-flops. S0 S1 S3 S2
01/0
10/0
01/1
10/1

30. Example: Vending Machine
Lecture
Digital Systems
Example: Vending Machine
Current States
Inputs
Next State
Output Y1 Y0 A B 1 X
State Table of the Vending Machine

31. Lecture
Digital Systems
Group Homework 9 (1/3)
Design a 3-bit counter that will deliver the output Y2Y1Y0 for every positive edge of the clock. If the input X is equal to 0, the count will stop, whereas if the input X is equal to 1, the count will proceed and repeat in a loop.
The type flip-flop to be used and the counting sequence is to be given on the next slide. ? Q Q’
FF2 Y2 X
FF1 Y1
FF0 Y0
Clock
Please write your Class number after your Student ID.
Deadline: 1 day before class.
Monday, 20 November 2017 (Class 2).
Tuesday, 21 November 2017 (Class 1).

32. Group Homework 9 (2/3) 1 000, 001, 010, 011, 100, 101, 110, 111 T R-S
Lecture
Digital Systems
Group Homework 9 (2/3)
Group
Counting Sequence Y2Y1Y0
FF2
FF1
FF0 1
000, 001, 010, 011, 100, 101, 110, 111 T
R-S 4 D 2
111, 110, 101, 100, 011, 010, 001, 000
J-K 5 3
000, 011, 110, 001, 100, 111, 010, 101 6
For group number distribution, see next slide.
Write the state diagram and the state table of your counter.
Write down the detailed steps of your design and submit the hardcopy.
Send the result file (***.atanua) to my address
Title of Digital Systems, Class Number, Group Number.
Body of Group members who contribute in making the homework.

33. Lecture
Digital Systems
Group Homework 9 (3/3)