1. OUT-OF-CLASS ACTIVITY CONSTRUCTOR FOR FLIPPED CLASSROOM
IDP in Educational Technology – IIT Bombay

2. Pinkesh V. Patel Binary Adder Circuit Digital Electronics Electrical
1st Year UG students
Dharmsinh Desai University, Nadiad
IDP in Educational Technology, IIT Bombay

3. Your Resource Creation Assignment 1
In TPS activity, students should able to learn about the design concept of binary adder digital circuit.
Key Concept: Concept of binary addition
Truth Table derivation
Boolean function reduction
Optimum digital circuit design of binary adder.
The current activity extends this Implementation to design 4-bit parallel adder. Also study the impact of carry propagation time on the same.
IDP in Educational Technology, IIT Bombay

4. Out-of-class Activity Design -1
Learning Objective(s) of Out-of-Class Activity:
At the end of watching the videos student should be able to,
Binary Addition Operation(Understand Level)
How to write Boolean expression from the truth table. (Understand level).
Sum of Product form – canonical form (Apply Level)
Utilization of Half & Full Adder (Apply Level)
Key Concept(s) to be covered:
Binary Addition & Truth Table
Boolean Equation Simplification
4-bit Number Addition
IDP in Educational Technology, IIT Bombay

5. Out-of-class Activity Design - 2
Uploaded Video URL
License of Video
CC-BY-SA (reuse allowed)
Duration of Screencast
Minutes
CONCEPT
VIDEO SEGMENT
DURATION
(in min)
2-bit Binary Addition
V1 - 0:00 – 5:24
5.24
3-bit Binary Addition
V2 - 5:24 – 9:26
4.02
4-bit Binary Number Addition
V3 - 9:26 – 11:11
1.85
IDP in Educational Technology, IIT Bombay

6. Out-of-class Activity Design - 3
Aligning Assessment with Learning Objective
Learning Objective
Assessment Strategy
Expected Duration
(in min)
Additional Instructions (if any)
Learner will be able to understand Binary Addition Operation
Q1. Differentiate Half & Full Adder.
Q2. What is truth table?
Q3. Perform the following binary addition, (A=101011, B=011101) A+B
4 minutes
Watch V1 & V3 and then answer Q1, Q2 & Q3
Boolean expression from the truth table
Q1. Design Circuit for Full Adder.
Q2.Realize the Full Adder by Means of two Half Adder.
8 minutes
Watch V2 then answer Q1 & Q2
IDP in Educational Technology, IIT Bombay

7. Out-of-class Activity Design - 3
Aligning Assessment with Learning Objective
Learning Objective
Assessment Strategy
Expected Duration
(in min)
Additional Instructions (if any)
Utilization of Half & Full Adder
Q1. Design 4-bit parallel adder circuit.
Q2. How the carry is propagated for the above design circuit.
Q3. Which factor decide the speed of 4-bit binary number adder.
7 minutes
Watch V3 then answer Q1,Q2 & Q3
Expected activity duration
19 Minutes
IDP in Educational Technology, IIT Bombay