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Published byLucas Moody Modified over 6 years ago
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Dr Stephen Bell Rutherford Appleton Laboratory 18/12/2013
IP Library Dr Stephen Bell Rutherford Appleton Laboratory 18/12/2013
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IP library -development and management
What is required for an IP Library: Documentation! Documentation! Documentation! EDA library database Common standard for designing of IP blocks Core supported tools set Acceptance criteria and peer review Revision control Storage and access
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EDA library database EDA library database should contain:
Description of block and it’s function Specification of IP across PVT corners Design database cell views and textual files Layout pinout/placement details (Hardblocks) Test benches to simulate/verify Synthesis/P&R scripts (Softblocks) Datasheets (Waveforms/measurements)
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EDA library database -analogue focused
Block cell views: schematic/layout/symbol/verilog(a/ams)/config/abstract Test benches used to characterised IP block Multi-testbench simulation environment: adexl Datasheet with simulation results automatically generated from ADEXL Files Liberty black box model(pin info/antenna) Verilog model(black box) Spice subcircuit (Pre/post-layout) for fast spice modelling LEF file for standalone P&R environment GDSII and layers file
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IP library structure Cell level View level Refs testbenches
Open Access IP Library Cell level IP_Block IP_BlockTB_AC IP_BlockTB_TRAN .. View level schematic schematic schematic constraints config config verilogA/AMS configPS .. symbol configAMS layout config= netlist view list control configPS=netlist for post layout configAMS= netlist for simulator extracted ADEXL Refs testbenches State files
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ADEXL view Parameters for Circuit Opt. Corners set for PVT
Multi-test env. Auto. gen. datasheets Documentation ADEXL State files Specifications Yield analysis
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Conclusions ADE XL/GXL provides:
Central location for storing simulation results and documentation Automatic generation of datasheets Specification driven environment Platform for retargeting/optimisation IP blocks
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