1. Sequential Circuit - Counter -

2. INTRODUCTION
A counter – a group of flip-flops connected together to perform counting operations.
The number of flip-flops used and the way in which they are connected determine the number of states (modulus).
Two broad categories according to the way they are clocked:
Asynchronous counter
Synchronous counter

3. Asynchronous counter

4. ASYNCHRONOUS COUNTER:
Don’t have fixed time relationship with each other.
Triggering don’t occur at the same time.
Don’t have a common clock pulse

5. 2-bit asynchronous counter
Notice that :
Main clock pulse only applied to FF0.
Clock for next FF, taken from previous complemented output ( Q ).
All inputs (J, K) are high (Vcc). [ output toggle at every +ve edge clock ]

6. The Timing diagram

7. The Binary State Sequence1 1 1 1
CLOCK PULSE Q1 Q0
Initially 1 2 3
4 (recycles)

8. Three-bit asynchronous binary counter and its timing diagram for one cycle.

9. The Binary State Sequence for a 3-bit Binary Counter
CLOCK PULSE Q2 Q1 Q0
Initially 1 2 3 4 5 6 7
8 (recycles)

10. Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.

11. Four-bit asynchronous binary counter and its timing diagram.

12. ASYNCHRONOUS DECADE COUNTER:
The modulus of a counter is the number of unique states that the counter will sequence through.
The maximum possible number of states (max modulus) is 2n . Where n is the number of flip-flops.
Counter can also be designed to have a number of states in their sequence that is less than the maximum of 2n. The resulting sequence is called truncated sequence.
Counter with ten states are called decade counter.
To obtain a truncated sequence it is necessary to force the counter to recycle before going through all of its possible states.

13. An asynchronously clocked decade counter
Read example 9-2 page 465!! Modulus 12

14. Comparison of 4-bit modulus 16 and modulus 10

15. Timing diagram
Modulus 16

16. For modulus 10, pay attention at clock 9 , and 10 of modulus 16
At clock 9, Q3..Q0 o/p = 1001 ( in decimal = 9)
For modulus 16
At clock 10, Q3..Q0 o/p = 1010 ( in decimal = 10).
Here Q3 = 1, Q1 = 1
For modulus 10
Q3 AND Q1 connected by NAND gate.
Means when Q1 =1 AND Q3 = 1, o/p of NAND = 0 
Happened at clock 10, Q1 = 1 AND Q3 = 1 Q0 Q1 Q2 Q3
Taken from modulus 16 o/p Q1 Q3

17. Here the o/p of NAND gate will fed into ACTIVE LOW input of CLR.
FF FF FF FF3
Here the o/p of NAND gate will fed into ACTIVE LOW input of CLR.
Since NAND o/p =0, the Flip-flop will be CLEARED.
This introduce glitch in the modulus 10 o/p.
Data transmission as descred above only happened in very short time glitch.
Tata being cleared at clock 10

18. The 74LS93A 4-bit asynchronous binary counter logic diagram
The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.)

19. Synchronous counter

20. SYNCHRONOUS COUNTER OPERATION A 2-bit synchronous binary counter.

21. Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal).

22. The Binary State Sequence1 1 1 1
CLOCK PULSE Q1 Q0
Initially 1 2 3
4 (recycles)

23. 3-bit synchronous binary counter modulo 7.

24. The Binary State Sequence for a 3-bit Binary Counter
CLOCK PULSE Q2 Q1 Q0
Initially 1 2 3 4 5 6 7
8 (recycles)

25. A 4-bit synchronous binary counter and timing diagram
A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas.

26. A 4-Bit Synchronous BCD Decade Counter (09).

27. The Binary State Sequence for BCD Decade Counter
CLOCK PULSE Q3 Q2 Q1 Q0
Initially 1 2 3 4 5 6 7 8 9
10 (recycles)

28. DESIGN OF SYNCHRONOUS COUNTERS General clocked sequential circuit.

29. Steps used in the design of sequential circuit
Specify the counter sequence and draw a state diagram
Derive a next-state table from the state diagram
Develop a transition table showing the flip-flop inputs required for each transition. The transition table is always the same for a given type of flip-flop
Transfer the J and K states from the transition table to Karnaugh maps. There is a Karnaugh map for each input of each flip-flop.
Group the Karnaugh map cells to generate and derive the logic expression for each flip-flop input.
Implement the expressions with combinational logic, and combine with the flip-flops to create the counter.

30. State diagram for a 3-bit Gray code counter.

31. Next-state table for a 3-bit Gray code counter.
Present State
Next State Q2 Q1 Q0 1

32. Transition Table for a J-K flip-flop
Output Transitions
Flip-flop Inputs QN
QN+1 J K  X 1
QN : present state
QN+1: next state
X: Don’t care

33. Karnaugh maps for present-state J and K inputs.

34. Three-bit Gray code counter.

35. Example: Design a counter with the irregular binary count sequence as shown in the state diagram. Use J-K flip-flops

36. Next-state table
Present State
Next State Q2 Q1 Q0 1

37. Transition Table for a J-K flip-flop
Output Transitions
Flip-flop Inputs QN
QN+1 J K  X 1

38. K-MAP

39. THE COUNTER CIRCUIT

40. Example : State diagram for a 3-bit up/down Gray code counter.

41. The 74HC163 4-bit synchronous binary counter
The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.)

42. Timing example for a 74HC163.

43. The 74LS160 synchronous BCD decade counter
The 74LS160 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.)

44. Timing example for a 74LS160.

45. UP/DOWN SYNCHRONOUS COUNTER A basic 3-bit up/down synchronous counter.

46. Timing Diagram

47. The 74HC190 up/down synchronous decade counter.

48. Timing example for a 74HC190.

49. J and K maps for Table 9-11. The UP/DOWN control input, Y, is treated as a fourth variable.

50. Three-bit up/down Gray code counter.

51. CASCADE COUNTERS
Two cascaded counters (all J and K inputs are HIGH).

52. A modulus-100 counter using two cascaded decade counters.

53. Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide- by-10 and divide-by-100 outputs.

54. Example: Determine the overall modulus of the two cascaded counter for (a) and (b)
For (a) the overall modulus for the 3 counter configuration is 8 x 12 x 16 = 1536 for (b) the overall modulus for the 4 counter configuration is 10 x 4 x 7 x 5 = 1400

55. A divide-by-100 counter using two 74LS160 decade counters.

56. A divide-by-40,000 counter using 74HC161 4-bit binary counters
A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D0 is the LSB in each counter).

57. Decoding of state 6 (110). COUNTER DECODING
* To determine when the counter is in a certain states in its sequence by using decoders or logic gates.
Decoding of state 6 (110).

58. A 3-bit counter with active-HIGH decoding of count 2 and count 7.

59. A basic decade (BCD) counter and decoder.

60. Outputs with glitches from the previous decoder
Outputs with glitches from the previous decoder. Glitch widths are exaggerated for illustration and are usually only a few nanoseconds wide.

61. The basic decade counter and decoder with strobing to eliminate glitches.

62. Strobed decoder outputs for the circuit

63. Simplified logic diagram for a 12-hour digital clock.

64. Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).

65. Logic diagram for hours counter and decoders
Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB.

66. Functional block diagram for parking garage control.

67. Logic diagram for modulus-100 up/down counter for automobile parking control.

68. Parallel-to-serial data conversion logic.

69. Example of parallel-to-serial conversion timing for the previous circuit

70. THANK YOU