1. I/O Standard Based Power Optimized Processor Register Design on Ultra Scale FPGA
Prabhat Ranjan Singh1, Bishwajeet Pandey2, Tanesh Kumar3 and Teerath Das4

2. NOMENCLATURE FPGA-Field Programmable Gate Array
HSTL-High Speed Transceiver Logic
LVCMOS-Low Voltage Complementary metal Oxide Semi Conductor.

3. INTRODUCTION
Selection of I/O standard plays a vital role in energy optimization of overall circuit design.
To match the impedance of transmission line of register and I/O port of register, we use different type of I/O standard such as HSTL, LVCMOS, and HSUL.
This design is implemented on 28nm Artix-7 FPGA, which supports HSTL, SSTL, LVCMOS and HSUL I/O Standard.

4. INTRODUCTION
The main motive of this work is to search energy efficient I/O standard on 28nm technology in order to fulfill our goal of energy optimized design of register first, energy optimized processor thereafter. ALU for arithmetic and logic operation, register for internal storage of CPU, memory for external storage of data and control unit for instruction of processor are integral part of any processor.
Energy efficiency of processor is related to power optimization of Memory, ALU, Register and Control unit.
In this work, power optimization of register is our design goal.

5. INTRODUCTION
Registers is used to hold information for data, address, buffer and type range.
It is located on different location in the CPU for storage purpose.
Memory Type Range Registers (MTRR), Memory Data Register, Memory Buffer Register, and Memory Address Register (MAR) are different types of register available in processor.
Extending the power optimized approach used in register to other component of processor will help us to achieve the goal of power optimized processor.

6. Top Level Schematic of 32-bit Register
Figure 2: 32-bit Register implemented in Xilinx ISE 14.6
This is 32-bit power optimized register, which work in serial input and serial output manner as it is using energy efficient I/O standard.

7. RTL Schematic of 32-bit Register
Figure 3: RTL Schematic of 32-bit Register
RTL schematic is register transfer level schematic.
It stores in NGR (Native Generic Register) file. In Figure3, there are 32 D flip flops.

8. Technology Schematic of 32-bit Register
Figure 4: Technology Schematic of 32-bit Register
Technology schematic is a Native Generic Circuit File of 32-bit register, as shown in Figure4, there are 32 Flip-flops/Latches, one Clock Buffers, 66 input/output Buffers(IO Buffers), 34 input buffer(IBUF) and 32 output Buffers.

9. Energy Frittering with LVCMOS Standard at 1000MHz
Clock
0.009
Leakage
0.081
0.083
0.086
0.090
Signal
0.002
IOs
0.100
0.134
0.237
0.403
It is observed that the energy requirement for clock energy, signals energy are same for all the four I/O standards.
There is an increase in I/O energy with the increase in voltage of I/O standard.
When register operates at 1000MHz, the reduction in I/O energy Frittering of LVCMOS15 is 25.37%, 57.80%, 75.18% lesser of LVCMOS18, LVCMOS25 and LVCMOS33 respectively.
Figure 6: IO Energy with Different Class of LVCMOS

10. Energy Frittering with LVCMOS Standard at 10 GHz18
LVCMOS25
LVCMOS33
Clock
0.092
Leakage
0.085
0.088
0.096
0.110
Signal
0.018
IOs
0.999
1.340
2.366
4.028
From Table 14, it is observed that LVCMOS15 is the least energy fritter and LVCMOS33 is the maximum energy fritter LVCMOS IO standard. When register is operates at 10000MHz, the reduction in I/O energy Frittering of LVCMOS15 is 25.44%, 57.77%, 75.19% lesser of LVCMOS18, LVCMOS25 and LVCMOS33 respectively.
Figure 7: IO Energy with Different Class of LVCMOS

11. Energy Consume with LVCMOS Standard at 100 GHz
Clock
0.920
Leakage
0.213
0.337
0.816
0.819
Signal
0.182
IOs
9.989
13.404
23.662
40.279
There is an increase in I/O energy with the increase in voltage of I/O standard.
The supply voltage of LVCMOS15, LVCMOS18, LVCMOS25 and LVCMOS33 is 1.5V, 1.8V, 2.5V and 3.3V respectively.
When register operates at MHz, the reduction in I/O energy Frittering of LVCMOS15 is 25.47%, 57.78%, 75.20% lesser of LVCMOS18, LVCMOS25 and LVCMOS33 respectively.
Figure 8: I/O Energy with Different LVCMOS

12. Energy Frittering with LVCMOS Standard at 1 THz
Clock
9.202
Leakage
0.812
0.813
0.816
0.819
Signal
1.818
IOs
99.886
when register operates at 1 THz, the reduction in I/O energy Frittering of LVCMOS15 is 25.48%, 57.78%, 75.20% lesser of LVCMOS18, LVCMOS25 and LVCMOS33 respectively.
Figure 9: I//O Energy with Different LVCMOS at 1THz

13. Energy Frittering with HSTL Standard at 1000MHz
From Table 17, HSTL_II I/O standards is the lowest energy fritter whereas HSTL_I_18 is the highest energy fritter.
When register operates at 1000MHz, the reduction in I/O energy Frittering of HSTL_II is 25.48%, 57.78%, 75.20% lesser of HSTL_I, HSTL_I_18 and HSTL_II_18 respectively.
Energy
HSTLI
HSTLII
HSTLI18
HSTLII18
Clock
0.009
Leakage
0.082
0.083
0.084
Signal
0.004
IOs
0.257
0.311
0.316
0.394

14. Energy Frittering with HSTL Standard at 10000MHz
HSTLI
HSTLII
HSTLI18
HSTLII18
Clock
0.092
Leakage
0.086
0.085
0.088
Signal
0.042
IOs
1.222
0.856
1.371
0.988
From Table 18, it is observed that HSTL_II I/O standards is the lowest I/O energy fritter whereas HSTL_I_18 I/O standards is the lowest I/O energy fritter.
When register operates at 10 GHz, the reduction in I/O energy Frittering of HSTL_II is 25.48%, 57.78%, 75.20% lesser of HSTL_I, HSTL_I_18 and HSTL_II_18 respectively.
Figure 11: I//O Energy with Different HSTL at 10000MHz

15. Conclusion
LVCMOS15 is the energy efficient I/O standard whereas LVCMOS33 is the worst energy fritter among the 4 different low voltage complementary metal oxide semiconductor is taken under consideration is this work.
There is theoretical reduction of 30.55%, 64.00%, and 79.34% in I/O energy which change in output driver supply voltage from 3.3V, 2.5V and 1.8V to 1.5V.
In practical we achieve following reduction with LVCMOS15 is 25.37%, 57.80%, 75.18% than LVCMOS18, LVCMOS25 and LVCMOS33 respectively. Our practical result is slightly lesser of the theoretical assumption due to other factor like resistance, airflow and capacitance.
In the same way, HSTL_II is the lowest energy fritter I/O standards whereas HSTL_I_18 is the highest energy fritter among all available 4 different HSTL I/O standards for 10000MHz, MHz and 1 THz.
HSTL_I I/O standards dissipates minimum energy whereas HSTL_II_18 dissipates maximum I/O energy among all available 4 different HSTL I/O standards for 1000MHz.

16. Future Scope This Design is implemented on 28nm FPGA.
There is an open scope to redesign this register on 16nm ultra scale FPGA in order to reduce area on FPGA and energy Frittering of register.
In this work, I/O standard is an effective technique to reduce energy Frittering of register. Therefore, I/O standard can be used to optimize energy Frittering of other component of processor namely ALU, Control Unit and Memory.

17. References
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