1. LHC BLM system: system overview
Christos Zamantzas
09/11/2017

2. Specification 5. USE OF THE BLM’S FOR MACHINE PROTECTION
The strategy for machine protection impacts on the BLM design in two ways, its time response and the reliability.
Protection of the machine from beam losses has two aspects:
• protection against beam losses that could lead to damage of equipment,
• protection against beam losses that could lead to a quench of a magnet.
Since a repair of superconducting magnets would take several weeks, the protection against damage has highest priority and damages should be strictly avoided (SIL 3, 1E-8 to 1E-7 1/h).
In case of a quench, the quench protection system would prevent equipment damage. However, the beam would be lost and re-establishing operation would take several hours. Therefore the number of quenches should be minimized
09/11/2017

3. LHC Beam Loss Monitoring System
Settings and Thresholds
Front-end CPU
Databases, fixed displays…
x27
Processing, Analysis & Decision
Combiner & Survey
Beam Loss Monitors
Acquisition & Digitisation
Beam Interlock System Interface
x16
x4000
x750
x400
x27
around the LHC ring
grouped in 8 points
Tunnel
Surface
09/11/2017

4. Tunnel Installation Detector positions Signal and HV distribution
ARC electronics
DS & LSS electronics
09/11/2017

5. Ionisation Chamber Low pass filter at the HV input
Stainless steal cylinder
Parallel Al electrodes distance 0.5 cm
Diameter 8.9 cm, Length 60 cm
Sensitive volume 1.5 l
Voltage 1.5 kV
Low pass filter at the HV input
Ion collection time 85 us
N2 gas filling at 1.1 bar
09/11/2017

6. Acquisition module Specifications: Components:
Radiation tolerant up to 500 Gy
Reliability level SIL3 (1E-7 to 1E-8 failure/h) to damage of equipment
Current measurement range 2.5pA to 1mA
Integration time of 40 us
Input protection
Current ~
Voltage ~
Redundant optical data transfer to surface
Test features for system check
Survey of the card voltage supplies
Survey of detector high voltage supply
Components:
8 inputs Current-to-Frequency Converter (COTS)
AD41240 ADC (EP-ESE)
LM4140 voltage reference
Antifuse FPGA for data collection
Redundant GOH from CMS (GOL from EP-ESE)
CRT910 Line driver (EP-ESE)
AD5346 DAC
09/11/2017

7. Measurement principle
Essentials of the input circuit:
Current to frequency converter (CFC)
Balanced charge integrator
No charge loss (“no blind time”)
Very large dynamic range
Output frequency depends on input current
Input Current
Output frequency
1mA
5MHz
1uA
5kHz
1nA
5Hz
1pA
5mHz
09/11/2017

8. Surface configuration4 1 3 2
FEC/CTRP – CPU / GMT timing
BOBR – BST timing
BLECS - Combiner & Survey
BLETC – Threshold Comparator
09/11/2017

9. Processing Module LEDs showing system and communication status
The BLM Mezzanine is hosting the receiver parts for four optical links. It handles the de-serialization and decoding of the optical gigabit data transmission lines in parallel and provides the received data to the DAB64x card’s FPGA device for processing.
Connector to program the FPGA & Configuration device.
LEMO connectors for accessing some FPGA I/Os.
The P0 connector is on a custom-made backplane.
It daisy-chains, the two beam permit lines and provide the beam energy data input.
E2000-APC input connections to four optical fibres.
09/11/2017

10. Real-Time Analysis of Data
Data-Combine
Applies merging algorithm for the ADC and the CFC data.
Filters noise.
Successive Running Sums (SRS)
Produces and maintains various histories of the received data in the form of Moving Sum Windows.
12 integration periods spanning from 40μs to 84s.
09/11/2017

11. Successive Running Sums (SRS)
Multi-point Shift Registers holds data
Successive calculation of Running Sums
Range 40μs - 84s (12 Running Sums)
Maximum values of the last second are continuously calculated and logged
Successive Running Sums configuration
Running Sums
Refreshing
Shift Register Name
Signal Name
bits used
40 μs
steps ms
40 μs steps 1
0.04
SR0
RS 01 20 2
0.08
RS 02 22 8
0.32
SR1
RS 03 16
0.64
RS 04 64
2.56
SR2
RS 05 26
256
10.24
RS 06
2048
81.92
SR3
RS 07 32
16384
655.36
RS 08
32768
SR4
RS 09 36
131072
RS 10
524288
SR5
RS 11 40
RS 12
09/11/2017

12. SRS and Threshold levels11 1 2 3 4 5 6 7 8 9 10
An error less than 20% in the approximation of the threshold lines is reached with 12 integration time windows and 32 energy steps
09/11/2017

13. Future Work
09/11/2017

14. LHC Beam Loss Monitoring System
on-going
done
on-going
Settings and Thresholds
Front-end CPU
Databases, fixed displays…
on-going
x27
Processing, Analysis & Decision OK OK
Combiner & Survey OK
Beam Loss Monitors
to start
Acquisition & Digitisation
Beam Interlock System Interface
x16
x4000
x750
x400
x27
around the LHC ring
grouped in 8 points
Tunnel
Surface
09/11/2017

15. VFC-HD module DDR3 Beam Synchronous Timing VME64x interface
Ethernet (White Rabbit)
P0 User defined connection
4 SFP for fast connections to the Front-ends
ARRIA V FPGA
HPC-FMC slot
Rear Transition Module connection
09/11/2017

16. Thank you