1. EE141
Chapter 3 VLSI Design
The Devices
March 28, 2003

2. Goal of this chapter
Present intuitive understanding of device operation
Introduction of basic device equations
Introduction of models for manual analysis
Introduction of models for SPICE simulation
Analysis of secondary and deep-sub-micron effects
Future trends

3. The Diode Mostly occurring as parasitic element in Digital ICs n p B A
SiO 2 Al
Cross-section of pn
-junction in an IC process
One-dimensional
representation
diode symbol
Mostly occurring as parasitic element in Digital ICs

4. Depletion Region

5. Diode Current

6. Models for Manual Analysis

7. Junction Capacitance

8. Secondary Effects Avalanche Breakdown 0.1 ) A ( I –0.1 –25.0 –15.0I D
–0.1
–25.0
–15.0
–5.0
5.0 V
(V) D
Avalanche Breakdown

9. Diode Model

10. SPICE MODELS
SPICE: Simulation Program with Integrated Circuit Emphasis, by UCB in early 1970’s.
Level 1: Long Channel Equations - Very Simple
Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations
Level 3: Semi-empirical - Based on curve fitting to measured devices
Level 4 (Berkeley Short-Channel IGFET Model, BSIM3v3): Empirical - Simple and Very Popular,.
Full-fledged BSIM3v3 model (denoted as LEVEL 49) covers over 200 parameters.

11. SPICE Parameters

12. What is a Transistor?
A Switch! |V GS |
An MOS Transistor

13. The MOS Transistor
Polysilicon
Aluminum/Cu

14. MOS Transistors - Types and SymbolsG G S S
NMOS
Enhancement
NMOS
Depletion D D G G B S S
NMOS with
PMOS
Enhancement
Bulk Contact

15. Threshold Voltage: Concept

16. The Threshold Voltage

17. The Body Effect

18. Current-Voltage Relations
0.5 1
1.5 2
2.5 3 4 5 6
x 10 -4 V DS
(V) I D
(A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive
Saturation
VDS = VGS - VT
Quadratic
Relationship

19. Transistor in Linear

20. Transistor in Saturation
Pinch-off

21. Current-Voltage Relations Long-Channel Device

22. A model for manual analysis

23. Current-Voltage Relations The Deep-Submicron Era-4 V DS
(V)
0.5 1
1.5 2
2.5
x 10 I D
(A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Early Saturation
Linear
Relationship

24. Velocity Saturation u ( m / s ) u = 10 x = 1.5 x (V/µm) 5 sat n c
Constant velocity
Constant mobility (slope = µ) x c
= 1.5 x
(V/µm)

25. Perspective I V Long-channel device V = V Short-channel device V V - VGS DD
Short-channel device V V
- V V
DSAT GS T DS

26. ID versus VGS linear quadratic quadratic Long Channel Short Channel
0.5 1
1.5 2
2.5 3 4 5 6
x 10 -4 V GS
(V) I D
(A)
0.5 1
1.5 2
2.5
x 10 -4 V GS
(V) I D
(A)
linear
quadratic
quadratic
Long Channel
Short Channel

27. ID versus VDS Resistive Saturation VDS = VGS - VT Long Channel
0.5 1
1.5 2
2.5 3 4 5 6
x 10 -4 V DS
(V) I D
(A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive
Saturation
VDS = VGS - VT -4 V DS
(V)
0.5 1
1.5 2
2.5
x 10 I D
(A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Long Channel
Short Channel

28. A unified model for manual analysisG B

29. Simple Model versus SPICE
0.5 1
1.5 2
2.5
x 10 -4
Velocity Saturated
Linear
Saturated
VDSAT=VGT
VDS=VDSAT
VDS=VGT
(A) I D V
(V) DS

30. A PMOS Transistor Assume all variables negative! -2.5 -2 -1.5 -1 -0.5
-0.8
-0.6
-0.4
-0.2
x 10 -4 V DS
(V) I D
(A)
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
Assume all variables
negative!
VGS = -2.5V

31. Transistor Model for Manual Analysis

32. The Transistor as a Switch

33. The Transistor as a Switch

34. The Transistor as a Switch

35. MOS Capacitances Dynamic Behavior

36. Dynamic Behavior of MOS Transistor

37. The Gate Capacitance x L Polysilicon gate Top view Gate-bulk overlapd L
Polysilicon gate
Top view
Gate-bulk
overlap
Source n +
Drain W t ox n +
Cross section L
Gate oxide

38. Gate Capacitance Cutoff Triode Saturation
Resistive
Saturation
Most important regions in digital design: saturation and cut-off

39. Gate Capacitance Capacitance as a function of VGS
(with VDS = 0)
Capacitance as a function of the degree of saturation

40. Measuring the Gate Cap

41. Diffusion Capacitance
Bottom
Side wall
Channel
Source N D
Channel-stop implant A 1
Substrate W x j L S

42. Capacitances in 0.25 mm CMOS process

43. The Sub-Micron MOS Transistor
Threshold Variations
Subthreshold Conduction
Parasitic Resistances

44. Threshold Variations V V Low V threshold Long-channel threshold VDS L
Threshold as a function of
Drain-induced barrier lowering
the length (for low V )
(for low L ) DS

45. Sub-Threshold Conduction
0.5 1
1.5 2
2.5 10
-12
-10 -8 -6 -4 -2 V GS
(V) I D
(A) VT
Linear
Exponential
Quadratic
The Slope Factor
S is DVGS for ID2/ID1 =10
Typical values for S:
mV/decade

46. Sub-Threshold ID vs VGS
VDS from 0 to 1.0V

47. Sub-Threshold ID vs VDS
VGS from 0 to 0.3V

48. Summary of MOSFET Operating Regions
Strong Inversion VGS > VT
Linear (Resistive)
VDS < VDSAT
Saturated (Constant Current)
VDS  VDSAT
Weak Inversion (Sub-Threshold) VGS  VT
Exponential in VGS with linear VDS dependence

49. Parasitic Resistances

50. Latch-up (Effect of Parasitic Resistance)

51. SPICE Transistors Parameters

52. MAIN MOS SPICE PARAMETERS

53. SPICE Parameters for Parasitics

54. SPICE Model for NMOS and PMOS

55. SPICE Deck for a CMOS Inverter

56. SPICE Simulation Result

57. Future Perspectives
25 nm FINFET MOS transistor

58. Summary
Transistor Modeling is important for CMOS circuit design (updated by IC manufacturing companies based on ongoing technologies).
SPICE parameters provide a good link between manufacturer and designers.
SPICE model/parameters need to be updated to reflect the behavior of the MOS in deep sub-micron technology.
Recently, capacitor/inductor modeling become important for Radio-frequency (RF) designs.