1. Implementing A Double-Buffered System
Chapter 8
C6000 Integration Workshop
Technical Training
Organization
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Copyright © 2005 Texas Instruments. All rights reserved.

2. Goals for Lab 8 McBSP EDMA CPU + Investigate System Timing
Rcv
RCVCHAN
ADC
gBufRcv R +
COPY R
Xmt
XMTCHAN
DAC
gBufXmt L
Investigate System Timing
Implement a Double Buffered System
Technical Training
Organization
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3. Outline What is “Real Time” ? Examine System Timing
Implement a Double-Buffered System
Lab 8 – Double-Buffered Audio Pass Thru
Technical Training
Organization
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4. What is Real Time ? tS In-0 In-1 Process-0 tp Out-0 Definitions
tp: Processing Time
ts: Sample Period (time between input samples)
Real Time: Generating an output before receiving the next input (tp < ts)
Latency: Time from input to output (in this case…tp)
This is a minimum latency system (no buffering), ideal for control systems, but is computationally inefficient.
Technical Training
Organization
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What kind of system did we use in lab7?

5. Lab 7 – Single Buffer System Timing
. . .
In-0
In-15
In-16 tS
Rcv Buffer 0-15
Process 0-15 tP
Xmt Buffer 0-15
Latency
. . .
Out-0
Out-15
Block must be processed before In-16 arrives
Processing time increases 16x due to buffer size
Time constraint is the same: one sample period
Computationally efficient, but increased latency
Technical Training
Organization
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Why did we have to decrease our buffer size to get lab 7 to work?

6. Why Did the Last Lab Break? (tP > tS)
. . .
In-0
In-31
In-32 tS
Rcv Buffer 0-31
Process 0-31 tp
Xmt Buffer 0-31
Latency
. . .
Out-0
Out-31
Processing 32 samples takes longer than processing 16
The time to process the samples hasn’t changed (tS)
There are 3 solutions to this problem
Decrease buffer size (we did this at the end of lab 7)
Decrease processing time (tP) with optimization
Increase the amount of available time for processing
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Let’s see what Solution 2 (optimization) can do for us…

7. Using Optimization to Buy Time
Time needed to process 16 sine samples*
No Opt
Opt (-gp –o3)
Fast RTS & Opt
C6713 (225 MHz)
2400 cycles
10.7 μs
1024 cycles
4.5 μs
Not Needed
C6416 (1 GHz)
9600 cycles
9.6 μs
8000 cycles
8 μs
3600 cycles
3.6 μs
Without Optimization, we don’t have enough time to process 32 samples (double the processing time)
The C6713 is much more efficient because it is floating-point
The Fast RTS (run-time support) library is an optimized floating point library for C64x and C62x
So, what is the 3rd solution?
* Approximate numbers obtained with CCS profiler.
The time to copy the data is NOT included.

8. 3. Double Buffer System Timing
. . .
In-0
In-15
In-31
tB = BUFFSIZE * tS tB
Rcv Buffer (Ping)
Rcv Buffer (Pong)
Rcv Buffer (Ping)
Process (Ping)
Process (Pong) tp
Xmt Buffer (Ping)
Latency
. . .
Out-0
Out-15
Time constraint is now buffer length (tB) (NOT sample period (tS))
Processing is the same as the single buffer system
Latency is increased, but it is deterministic
Simultaneous receive, process, transmit
Also called Ping/Pong buffering
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How do we implement a double buffered system?

9. Implementing a Double Buffer System (1)
Add a second buffer to receive and transmit:
P i n g
P i n g
gBufferRcv
gBufferXmt
P o n g
P o n g
In the HWI, add a variable to check status of ping/pong:
if (pingpong == 0) {
copy RcvPing to XmtPing
pingpong = 1; }
else {
copy RcvPong to XmtPong
pingpong = 0; }
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10. Implementing a Double Buffer System (2)
For the EDMA, we need to create two reload entries (ping and pong) for both receive and transmit (receive only shown below):
Receive Ch (init)
RcvPong
RcvPing
Opt (same)
Opt (same)
Opt (same)
Src = DRR
Src = DRR
Src = DRR
Cnt = BUFFSIZE
Cnt = BUFFSIZE
Cnt = BUFFSIZE
Dst = Ping
Dst = Pong
Dst = Ping
Index
Index
Index
Cnt Rld
Link=Pong
Cnt Rld
Link=Ping
Cnt Rld
Link=Pong
Psuedo Code
Allocate reload entries for Ping and Pong
Src = DRR (McBSP0)
EDMA_config (…)
Link: channel  Pong, Pong  Ping, Ping  Pong
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11. Lab 8 – Double Buffer Audio Pass Thru
McBSP
EDMA
CPU L
Rcv
RCVCHAN
ADC
gBufRcv R +
COPY R
Xmt
XMTCHAN
DAC
gBufXmt L
Technical Training
Organization
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Implement a Double Buffered System

12. Technical Training
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